Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495558
Ehsan Aerabi, A. E. Amirouche, Houda Ferradi, R. Géraud, D. Naccache, J. Vuillemin
Over the last twenty years, the research community has devised sophisticated methods for retrieving secret information from side-channel emanations, and for resisting such attacks. This paper introduces a new CPU architecture called the Conjoined Microprocessor (CμP). The CμP can randomly interleave the execution of two programs at very low extra hardware cost. We developed for the CμP a preprocessor tool that turns a target algorithm into two (or more) separate queues like Q0 and Q1 that can run in alternation. Q0 and Q1 fulfill the same operation as the original target algorithm. Power-analysis resistance is achieved by randomly alternating the execution of Q0 and Q1, with different runs resulting in different interleavings. Experiments reveal that this architecture is indeed effective against CPA.
{"title":"The Conjoined Microprocessor","authors":"Ehsan Aerabi, A. E. Amirouche, Houda Ferradi, R. Géraud, D. Naccache, J. Vuillemin","doi":"10.1109/HST.2016.7495558","DOIUrl":"https://doi.org/10.1109/HST.2016.7495558","url":null,"abstract":"Over the last twenty years, the research community has devised sophisticated methods for retrieving secret information from side-channel emanations, and for resisting such attacks. This paper introduces a new CPU architecture called the Conjoined Microprocessor (CμP). The CμP can randomly interleave the execution of two programs at very low extra hardware cost. We developed for the CμP a preprocessor tool that turns a target algorithm into two (or more) separate queues like Q0 and Q1 that can run in alternation. Q0 and Q1 fulfill the same operation as the original target algorithm. Power-analysis resistance is achieved by randomly alternating the execution of Q0 and Q1, with different runs resulting in different interleavings. Experiments reveal that this architecture is indeed effective against CPA.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495550
Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, S. Kundu
Physically unclonable functions (PUFs) are emerging as hardware primitives for key-generation and light-weight authentication. Strong PUFs represent a variant of PUFs which respond to a user challenge with a response determined by its unique manufacturing process variations. Unfortunately many of the Strong PUFs have been shown to be vulnerable to model building attacks when an attacker has access to challenge and response pairs. In mounting a model building attack, typically machine learning is used to build a software model to forge the PUF. Researchers have long been interested in designing Strong PUFs that are resistant to model building attacks. However, with innovations in application of machine learning, nearly all Strong PUFs presented in the literature have been broken. In this paper, first we present results from a set of experiments designed to show that if certain randomness properties can be met, cascaded structure based Strong PUFs can indeed be made machine learning (ML) attack resistant against known ML attacks. Next we conduct machine learning experiments on an abstract PUF model using Support Vector Machines, Logistic Regression, Bagging, Boosting and Evolutionary techniques to establish criteria for machine learning resistant Strong PUF design. This paper does not suggest how to harvest the process variation, which remains within the purview of a circuit designer; rather it suggests what properties of the building blocks to aim for towards building a machine learning resistant Strong PUF - thus paving the path for a systematic design approach.
{"title":"Machine learning resistant strong PUF: Possible or a pipe dream?","authors":"Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, S. Kundu","doi":"10.1109/HST.2016.7495550","DOIUrl":"https://doi.org/10.1109/HST.2016.7495550","url":null,"abstract":"Physically unclonable functions (PUFs) are emerging as hardware primitives for key-generation and light-weight authentication. Strong PUFs represent a variant of PUFs which respond to a user challenge with a response determined by its unique manufacturing process variations. Unfortunately many of the Strong PUFs have been shown to be vulnerable to model building attacks when an attacker has access to challenge and response pairs. In mounting a model building attack, typically machine learning is used to build a software model to forge the PUF. Researchers have long been interested in designing Strong PUFs that are resistant to model building attacks. However, with innovations in application of machine learning, nearly all Strong PUFs presented in the literature have been broken. In this paper, first we present results from a set of experiments designed to show that if certain randomness properties can be met, cascaded structure based Strong PUFs can indeed be made machine learning (ML) attack resistant against known ML attacks. Next we conduct machine learning experiments on an abstract PUF model using Support Vector Machines, Logistic Regression, Bagging, Boosting and Evolutionary techniques to establish criteria for machine learning resistant Strong PUF design. This paper does not suggest how to harvest the process variation, which remains within the purview of a circuit designer; rather it suggests what properties of the building blocks to aim for towards building a machine learning resistant Strong PUF - thus paving the path for a systematic design approach.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126650969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495571
Maxime Lecomte, J. Fournier, P. Maurine
With the outsourcing of the integrated circuit (IC) manufacturing, embedded systems faces threats as Hardware Trojan. This paper presents a characterization of a Hardware Trojan detection method introduced in a former work. In this work, a network of sensors is uniformly spread over the IC surface to monitor locally the inner supply voltage. By conducting an analysis by lot, the authors are able to get rid of the main problem of Hardware Trojan detection: the effect of intra-die and inter-die process variations. In this paper, an analysis of the spatial coverage of the method is made experimentally on a set of FPGA boards. From the obtained results, a modification of the used sensor is proposed as well as an adaptive distinguisher which aims at reducing the false positive rate. These two improvements are also experimentally tested and validated with the same set of FPGA boards.
{"title":"Granularity and detection capability of an adaptive embedded Hardware Trojan detection system","authors":"Maxime Lecomte, J. Fournier, P. Maurine","doi":"10.1109/HST.2016.7495571","DOIUrl":"https://doi.org/10.1109/HST.2016.7495571","url":null,"abstract":"With the outsourcing of the integrated circuit (IC) manufacturing, embedded systems faces threats as Hardware Trojan. This paper presents a characterization of a Hardware Trojan detection method introduced in a former work. In this work, a network of sensors is uniformly spread over the IC surface to monitor locally the inner supply voltage. By conducting an analysis by lot, the authors are able to get rid of the main problem of Hardware Trojan detection: the effect of intra-die and inter-die process variations. In this paper, an analysis of the spatial coverage of the method is made experimentally on a set of FPGA boards. From the obtained results, a modification of the used sensor is proposed as well as an adaptive distinguisher which aims at reducing the false positive rate. These two improvements are also experimentally tested and validated with the same set of FPGA boards.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114409111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495588
Muhammad Yasin, Bodhisatwa Mazumdar, J. Rajendran, O. Sinanoglu
Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.
{"title":"SARLock: SAT attack resistant logic locking","authors":"Muhammad Yasin, Bodhisatwa Mazumdar, J. Rajendran, O. Sinanoglu","doi":"10.1109/HST.2016.7495588","DOIUrl":"https://doi.org/10.1109/HST.2016.7495588","url":null,"abstract":"Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy, hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken multiple attempts in breaking logic locking techniques and recovering its secret key. A Boolean Satisfiability (SAT) based attack has been recently presented that breaks all the existing combinational logic locking techniques. In this paper, we develop a lightweight countermeasure against this and other attacks that aim at gradually pruning the key search space. Our proposed logic locking technique, referred to as SARLock, maximizes the required number of distinguishing input patterns to recover the secret key. SARLock thwarts the SAT attack by rendering the attack effort exponential in the number of bits in the secret key, while its overhead grows only linearly.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124375810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495556
S. Banik, A. Bogdanov, F. Regazzoni, Takanori Isobe, Harunaga Hiwatari, T. Akishita
Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60% while incurring only a minimal overhead in hardware.
{"title":"Round gating for low energy block ciphers","authors":"S. Banik, A. Bogdanov, F. Regazzoni, Takanori Isobe, Harunaga Hiwatari, T. Akishita","doi":"10.1109/HST.2016.7495556","DOIUrl":"https://doi.org/10.1109/HST.2016.7495556","url":null,"abstract":"Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60% while incurring only a minimal overhead in hardware.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117296118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495570
Johannes Bauer, Sebastian Schinzel, F. Freiling, Andreas Dewald
We present a new class of covert channels which can be created by utilizing common hardware but that cannot be detected by such. Our idea is to abuse anti-EMI features of a processor to create a covert channel on the physical layer. Thus, the sender uses the invariants in how digital signals are encoded over analog channels to covertly transport information. This leaked data is present on the wire bound connections of the compromised device, but is also by definition present in the vicinity of the device and can be picked up by radio equipment. As the covert channel is present only on the physical layer, the data on all layers above, as well as the timing behavior on those layers is indistinguishable from uncompromised devices.
{"title":"Information leakage behind the curtain: Abusing anti-EMI features for covert communication","authors":"Johannes Bauer, Sebastian Schinzel, F. Freiling, Andreas Dewald","doi":"10.1109/HST.2016.7495570","DOIUrl":"https://doi.org/10.1109/HST.2016.7495570","url":null,"abstract":"We present a new class of covert channels which can be created by utilizing common hardware but that cannot be detected by such. Our idea is to abuse anti-EMI features of a processor to create a covert channel on the physical layer. Thus, the sender uses the invariants in how digital signals are encoded over analog channels to covertly transport information. This leaked data is present on the wire bound connections of the compromised device, but is also by definition present in the vicinity of the device and can be picked up by radio equipment. As the covert channel is present only on the physical layer, the data on all layers above, as well as the timing behavior on those layers is indistinguishable from uncompromised devices.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129062341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495572
Ryan L. Helinski, E. I. Cole, G. Robertson, Jonathan Woodbridge, L. Pierson
The microelectronics industry seeks screening tools that can be used to verify the origin of and track integrated circuits (ICs) throughout their lifecycle. Embedded circuits that measure process variation of an IC are well known. This paper adds to previous work using these circuits for studying manufacturer characteristics on final product ICs, particularly for the purpose of developing and verifying a signature for a microelectronics manufacturing facility (fab). We present the design, measurements and analysis of 159 silicon ICs which were built as a proof of concept for this purpose. 80 copies of our proof of concept IC were built at one fab, and 80 more copies were built across two lots at a second fab. Using these ICs, our prototype circuits allowed us to distinguish these two fabs with up to 98.7% accuracy and also distinguish the two lots from the second fab with up to 98.8% accuracy.
{"title":"Electronic forensic techniques for manufacturer attribution","authors":"Ryan L. Helinski, E. I. Cole, G. Robertson, Jonathan Woodbridge, L. Pierson","doi":"10.1109/HST.2016.7495572","DOIUrl":"https://doi.org/10.1109/HST.2016.7495572","url":null,"abstract":"The microelectronics industry seeks screening tools that can be used to verify the origin of and track integrated circuits (ICs) throughout their lifecycle. Embedded circuits that measure process variation of an IC are well known. This paper adds to previous work using these circuits for studying manufacturer characteristics on final product ICs, particularly for the purpose of developing and verifying a signature for a microelectronics manufacturing facility (fab). We present the design, measurements and analysis of 159 silicon ICs which were built as a proof of concept for this purpose. 80 copies of our proof of concept IC were built at one fab, and 80 more copies were built across two lots at a second fab. Using these ICs, our prototype circuits allowed us to distinguish these two fabs with up to 98.7% accuracy and also distinguish the two lots from the second fab with up to 98.8% accuracy.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127179478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495560
Jacob Couch, Elizabeth Reilly, Morgan Schuyler, Bradley Barrett
Design recovery is commonly conducted across many different platforms to gain knowledge about the underlying internals of a system. In this paper, a concept of segmentation and fuzzy matching is introduced to identify IP blocks within a design. Through this process, known IP blocks, especially in optimized ASIC and FPGA designs, can be identified within a netlist. Furthermore, these algorithms are computationally more efficient in comparison to the traditional subgraph isomorphism problem.
{"title":"Functional block identification in circuit design recovery","authors":"Jacob Couch, Elizabeth Reilly, Morgan Schuyler, Bradley Barrett","doi":"10.1109/HST.2016.7495560","DOIUrl":"https://doi.org/10.1109/HST.2016.7495560","url":null,"abstract":"Design recovery is commonly conducted across many different platforms to gain knowledge about the underlying internals of a system. In this paper, a concept of segmentation and fuzzy matching is introduced to identify IP blocks within a design. Through this process, known IP blocks, especially in optimized ASIC and FPGA designs, can be identified within a netlist. Furthermore, these algorithms are computationally more efficient in comparison to the traditional subgraph isomorphism problem.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495576
Rui Qiao, Mark Seaborn
Rowhammer is a hardware bug identified in recent commodity DRAMs: repeated row activations can cause bit flips in adjacent rows. Rowhammer has been recognized as both a reliability and security issue. And it is a classic example that layered abstractions and trust (in this case, virtual memory) can be broken from hardware level. Previous rowhammer attacks either rely on rarely used special instructions or complicated memory access patterns. In this paper, we propose a new approach for rowhammer that is based on x86 non-temporal instructions. This approach bypasses existing rowhammer defense and is much less constrained for a more challenging task: remote rowhammer attacks, i.e., triggering rowhammer with existing, benign code. Moreover, we extend our approach and identify libc memset and memcpy functions as a new rowhammer primitive. Our discussions on rowhammer protection suggest that it is critical to understand this new threat to be able to defend in depth.
{"title":"A new approach for rowhammer attacks","authors":"Rui Qiao, Mark Seaborn","doi":"10.1109/HST.2016.7495576","DOIUrl":"https://doi.org/10.1109/HST.2016.7495576","url":null,"abstract":"Rowhammer is a hardware bug identified in recent commodity DRAMs: repeated row activations can cause bit flips in adjacent rows. Rowhammer has been recognized as both a reliability and security issue. And it is a classic example that layered abstractions and trust (in this case, virtual memory) can be broken from hardware level. Previous rowhammer attacks either rely on rarely used special instructions or complicated memory access patterns. In this paper, we propose a new approach for rowhammer that is based on x86 non-temporal instructions. This approach bypasses existing rowhammer defense and is much less constrained for a more challenging task: remote rowhammer attacks, i.e., triggering rowhammer with existing, benign code. Moreover, we extend our approach and identify libc memset and memcpy functions as a new rowhammer primitive. Our discussions on rowhammer protection suggest that it is critical to understand this new threat to be able to defend in depth.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"398 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-03DOI: 10.1109/HST.2016.7495559
S. Banik, A. Bogdanov, Kazuhiko Minematsu
The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.
{"title":"Low-area hardware implementations of CLOC, SILC and AES-OTR","authors":"S. Banik, A. Bogdanov, Kazuhiko Minematsu","doi":"10.1109/HST.2016.7495559","DOIUrl":"https://doi.org/10.1109/HST.2016.7495559","url":null,"abstract":"The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit serialized AES circuit. In this context we investigate three authenticated encryption modes CLOC, SILC and AES-OTR. Using the standard cell library of the STM 90nm process, we implemented CLOC and SILC with around 3110 GE whereas AES-OTR was implemented with around 4720 GE.","PeriodicalId":194799,"journal":{"name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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