Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670558
J. Naderman, F. W. Ragay, D. de Vries, A. van Eck, J. Van de Water
Backside scanning acoustic tomography (SCAT) images have been correlated to alloy morphology (cross-section) and composition data (stochiometry) to model the /spl Theta//sub JC/ degradation for surface mounted device packaged power ICs as a function of the temperature cycling range. We find that an appropriate setting of the die attach process can suppress needle-shaped Cu/sub 3/Sn in favor of roughly spheroidal Cu/sub 6/Sn/sub 5/. We derived from the degradation of /spl Theta//sub JC/ during thermal cycling stress tests with different temperature swings, an acceleration factor which can be described by the Coffin-Manson law. The fitting parameter q in this formula is 9.35 for the new improved setting of the die attach process when the HSOP package is used. Finally, a maximum /spl Theta//sub JC/ degradation of 0.34 K/W based on the normal distribution approach results in a lifetime of 12 years. When a customer requires a maximum /spl Theta//sub JC/ of 2.0 K/W at the end of life, 50 years can be guaranteed.
{"title":"Thermal resistance degradation of alloy die attached power devices during thermal cycling","authors":"J. Naderman, F. W. Ragay, D. de Vries, A. van Eck, J. Van de Water","doi":"10.1109/RELPHY.1998.670558","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670558","url":null,"abstract":"Backside scanning acoustic tomography (SCAT) images have been correlated to alloy morphology (cross-section) and composition data (stochiometry) to model the /spl Theta//sub JC/ degradation for surface mounted device packaged power ICs as a function of the temperature cycling range. We find that an appropriate setting of the die attach process can suppress needle-shaped Cu/sub 3/Sn in favor of roughly spheroidal Cu/sub 6/Sn/sub 5/. We derived from the degradation of /spl Theta//sub JC/ during thermal cycling stress tests with different temperature swings, an acceleration factor which can be described by the Coffin-Manson law. The fitting parameter q in this formula is 9.35 for the new improved setting of the die attach process when the HSOP package is used. Finally, a maximum /spl Theta//sub JC/ degradation of 0.34 K/W based on the normal distribution approach results in a lifetime of 12 years. When a customer requires a maximum /spl Theta//sub JC/ of 2.0 K/W at the end of life, 50 years can be guaranteed.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121275793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670661
T. Ushiki, Mo-Chiun Yu, K. Kawai, T. Shinohara, K. Ino, M. Morita, T. Ohmi
The effects of ion species in the sputter deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputter deposition for gate electrode formation makes it possible to improve the gate oxide reliability. The Xe plasma process exhibits 1.5 times higher breakdown field and 5 times higher 50%-charge-to-breakdown (Q/sub BD/). In the gate-metal sputter deposition process, the physical bombardment of energetic ions causes generation of hole traps in the gate oxide, resulting in lower gate oxide reliability. A simplified model providing a better understanding of the empirical relationship between the gate oxide damage and the ion bombardment energy in the gate-metal sputter deposition process is also presented.
{"title":"Reduction of plasma-induced gate oxide damage using low-energy large-mass ion bombardment in gate-metal sputtering deposition","authors":"T. Ushiki, Mo-Chiun Yu, K. Kawai, T. Shinohara, K. Ino, M. Morita, T. Ohmi","doi":"10.1109/RELPHY.1998.670661","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670661","url":null,"abstract":"The effects of ion species in the sputter deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputter deposition for gate electrode formation makes it possible to improve the gate oxide reliability. The Xe plasma process exhibits 1.5 times higher breakdown field and 5 times higher 50%-charge-to-breakdown (Q/sub BD/). In the gate-metal sputter deposition process, the physical bombardment of energetic ions causes generation of hole traps in the gate oxide, resulting in lower gate oxide reliability. A simplified model providing a better understanding of the empirical relationship between the gate oxide damage and the ion bombardment energy in the gate-metal sputter deposition process is also presented.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122099109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670659
S. Voldman, R. Gauthier, D. Reinhart, K. Morrisseau
High-current phenomena and electrostatic discharge (ESD) in both aluminum and copper interconnects using transmission line pulse (TLP) testing are reported. Critical current density-to-failure, J/sub crit/, is evaluated as a function of pulse width for both wire and via structures. Experimental results demonstrate that copper-based interconnects have superior ESD robustness compared to aluminum-based interconnects.
{"title":"High-current transmission line pulse characterization of aluminum and copper interconnects for advanced CMOS semiconductor technologies","authors":"S. Voldman, R. Gauthier, D. Reinhart, K. Morrisseau","doi":"10.1109/RELPHY.1998.670659","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670659","url":null,"abstract":"High-current phenomena and electrostatic discharge (ESD) in both aluminum and copper interconnects using transmission line pulse (TLP) testing are reported. Critical current density-to-failure, J/sub crit/, is evaluated as a function of pulse width for both wire and via structures. Experimental results demonstrate that copper-based interconnects have superior ESD robustness compared to aluminum-based interconnects.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125370970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670671
J. van der Pol, E. Ooms, T. Van 't Hof, F. Kuper
This paper addresses the question of under what conditions burn-in can be eliminated. Based on data of more than 30 million sold devices, the effect of screening of latent defects at electrical test on product reliability has been investigated. The results are combined with the yield-reliability relation and an experimentally determined failure rate time evolution, yielding a model that allows determination of the sense or nonsense of burn-in or screens at electrical test quantitatively. The model predictions are in good agreement with experimental data. Furthermore, for typical operating conditions, high yielding batches show a better long term reliability than low yielding batches even if the latter have been subjected to burn-in. It is also shown that voltage stresses, distribution tests and IDDQ screens can be good alternatives to burn-in.
{"title":"Impact of screening of latent defects at electrical test on the yield-reliability relation and application to burn-in elimination","authors":"J. van der Pol, E. Ooms, T. Van 't Hof, F. Kuper","doi":"10.1109/RELPHY.1998.670671","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670671","url":null,"abstract":"This paper addresses the question of under what conditions burn-in can be eliminated. Based on data of more than 30 million sold devices, the effect of screening of latent defects at electrical test on product reliability has been investigated. The results are combined with the yield-reliability relation and an experimentally determined failure rate time evolution, yielding a model that allows determination of the sense or nonsense of burn-in or screens at electrical test quantitatively. The model predictions are in good agreement with experimental data. Furthermore, for typical operating conditions, high yielding batches show a better long term reliability than low yielding batches even if the latter have been subjected to burn-in. It is also shown that voltage stresses, distribution tests and IDDQ screens can be good alternatives to burn-in.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670665
M. Hosaka, T. Kouno, Y. Hayakawa, H. Niwa, M. Yamada
Electromigration lifetime tests on TiN-Ti-AlCu-TiN-Ti stacked structures with various upper Ti film thicknesses have been carried out on two-level interconnect structures connected with W-plugs. We found that a high electromigration resistance was obtained with thin Ti, resulting in an island shaped Al/sub 3/Ti intermetallic. This result is inconsistent with a well-known bypass model. We propose a new model in which the Al/sub 3/Ti-Al interface mass transport is faster than that of others.
{"title":"Ti layer thickness dependence on electromigration performance of Ti-AlCu metallization","authors":"M. Hosaka, T. Kouno, Y. Hayakawa, H. Niwa, M. Yamada","doi":"10.1109/RELPHY.1998.670665","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670665","url":null,"abstract":"Electromigration lifetime tests on TiN-Ti-AlCu-TiN-Ti stacked structures with various upper Ti film thicknesses have been carried out on two-level interconnect structures connected with W-plugs. We found that a high electromigration resistance was obtained with thin Ti, resulting in an island shaped Al/sub 3/Ti intermetallic. This result is inconsistent with a well-known bypass model. We propose a new model in which the Al/sub 3/Ti-Al interface mass transport is faster than that of others.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116029451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670658
K. Banerjee, C. Hu, A. Amerasekera, J. Kittl
Characterization and modeling of high current conduction in TiSi/sub 2/ and CoSi/sub 2/ films formed on n/sup +/-Si and n/sup +/ poly-Si under DC and pulsed stress conditions is reported for the first time. High current conductance of silicides is shown to be strongly affected by the technology and process conditions. The nonlinear I-V characteristics of silicide films under DC and pulsed high current stress has been modeled and the nonlinearity has been shown to be due to self-heating. Two physical parameters, B and /spl lambda/, associated with DC and pulsed current stress, have been shown to be able to describe the sensitivity of the films to high current conduction. At high currents, an abrupt lowering of the resistance of the silicided structures is observed. Detailed analysis of the evolution of this resistance drop has been made. It is shown that the cause is related to the melting of the structures, which also causes degradation in the post-stress silicide film resistance. The critical current for these failures has been shown to be strongly influenced by the silicide film width and the time duration of the pulse. CoSi/sub 2/ films and films on poly-Si are shown to be more sensitive to high current conduction and degradation.
{"title":"High current effects in silicide films for sub-0.25 /spl mu/m VLSI technologies","authors":"K. Banerjee, C. Hu, A. Amerasekera, J. Kittl","doi":"10.1109/RELPHY.1998.670658","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670658","url":null,"abstract":"Characterization and modeling of high current conduction in TiSi/sub 2/ and CoSi/sub 2/ films formed on n/sup +/-Si and n/sup +/ poly-Si under DC and pulsed stress conditions is reported for the first time. High current conductance of silicides is shown to be strongly affected by the technology and process conditions. The nonlinear I-V characteristics of silicide films under DC and pulsed high current stress has been modeled and the nonlinearity has been shown to be due to self-heating. Two physical parameters, B and /spl lambda/, associated with DC and pulsed current stress, have been shown to be able to describe the sensitivity of the films to high current conduction. At high currents, an abrupt lowering of the resistance of the silicided structures is observed. Detailed analysis of the evolution of this resistance drop has been made. It is shown that the cause is related to the melting of the structures, which also causes degradation in the post-stress silicide film resistance. The critical current for these failures has been shown to be strongly influenced by the silicide film width and the time duration of the pulse. CoSi/sub 2/ films and films on poly-Si are shown to be more sensitive to high current conduction and degradation.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133716700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670554
B. Euzent, B. K. Kawanami, S. Lau
There have been numerous studies of delamination induced failures after reflow soldering of surface mount devices. However, most of these studies have concentrated on packages with less than 100 pins with die smaller than 100 mm/sup 2/. In this paper, we examine the failure mechanism associated with larger die in plastic quad flatpacks (PQFPs) and thermally enhanced PQFPs with up to 304 pins and die area up to 212 mm/sup 2/. The degradation in performance with increased reflow soldering temperature and absorbed moisture is characterized, and techniques to improve performance in reflow soldering from both the integrated circuit and printed circuit board perspective are discussed.
{"title":"Critical parameters for reliable surface mounting of high pincount packages","authors":"B. Euzent, B. K. Kawanami, S. Lau","doi":"10.1109/RELPHY.1998.670554","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670554","url":null,"abstract":"There have been numerous studies of delamination induced failures after reflow soldering of surface mount devices. However, most of these studies have concentrated on packages with less than 100 pins with die smaller than 100 mm/sup 2/. In this paper, we examine the failure mechanism associated with larger die in plastic quad flatpacks (PQFPs) and thermally enhanced PQFPs with up to 304 pins and die area up to 212 mm/sup 2/. The degradation in performance with increased reflow soldering temperature and absorbed moisture is characterized, and techniques to improve performance in reflow soldering from both the integrated circuit and printed circuit board perspective are discussed.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670490
A. Olbrich, B. Ebersberger, C. Boit
Atomic force microscopy using with a conductive tip and a highly sensitive preamplifier is used for Fowler-Nordheim (FN) current measurements in the sub-pA range on various thin MOS gate and EEPROM tunneling oxides. Simultaneously with the oxide topography, local oxide thinning and electrically weak spots are detected quantitatively on a nanometer scale length in two dimensions. From the FN-fits to the microscopic I-V measurements, the effective area involved in the tunneling process (50-250 nm/sup 2/) and the local oxide thickness can be determined. The microscopic behaviour agrees excellently with macroscopic I-V curves so that the method can be correlated with standard reliability tests. Since the measurements are performed on the bare oxide surface, the method is suitable for in-line monitoring.
{"title":"Nanoscale electrical characterization of thin oxides with conducting atomic force microscopy","authors":"A. Olbrich, B. Ebersberger, C. Boit","doi":"10.1109/RELPHY.1998.670490","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670490","url":null,"abstract":"Atomic force microscopy using with a conductive tip and a highly sensitive preamplifier is used for Fowler-Nordheim (FN) current measurements in the sub-pA range on various thin MOS gate and EEPROM tunneling oxides. Simultaneously with the oxide topography, local oxide thinning and electrically weak spots are detected quantitatively on a nanometer scale length in two dimensions. From the FN-fits to the microscopic I-V measurements, the effective area involved in the tunneling process (50-250 nm/sup 2/) and the local oxide thickness can be determined. The microscopic behaviour agrees excellently with macroscopic I-V curves so that the method can be correlated with standard reliability tests. Since the measurements are performed on the bare oxide surface, the method is suitable for in-line monitoring.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133985074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670439
K. Takeda, K. Hinode, I. Oodake, N. Oohashi, H. Yamaguchi
Time-dependent dielectric breakdown (TDDB) of MIS and MIM capacitors with Cu electrodes is investigated. The dielectric breakdown lifetime strongly depends on (1) the material and (2) the electric field strength of the dielectrics in contact with the Cu anode, while the dependence of the TDDB lifetime on the dielectric thickness and the capacitor structure (single-layer or multilayer) is small. In the case of the applied voltage and the total thickness of the dielectrics being constant, the layered SiN-SiO/sub 2/ structure with thinner p-SiN has higher resistance to dielectric breakdown than that of a monolayer structure (SiN, SiO/sub 2/). This higher resistance to breakdown is because of the higher dielectric constant and the higher TDDB endurance of SiN.
{"title":"Enhanced dielectric breakdown lifetime of the copper/silicon nitride/silicon dioxide structure","authors":"K. Takeda, K. Hinode, I. Oodake, N. Oohashi, H. Yamaguchi","doi":"10.1109/RELPHY.1998.670439","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670439","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) of MIS and MIM capacitors with Cu electrodes is investigated. The dielectric breakdown lifetime strongly depends on (1) the material and (2) the electric field strength of the dielectrics in contact with the Cu anode, while the dependence of the TDDB lifetime on the dielectric thickness and the capacitor structure (single-layer or multilayer) is small. In the case of the applied voltage and the total thickness of the dielectrics being constant, the layered SiN-SiO/sub 2/ structure with thinner p-SiN has higher resistance to dielectric breakdown than that of a monolayer structure (SiN, SiO/sub 2/). This higher resistance to breakdown is because of the higher dielectric constant and the higher TDDB endurance of SiN.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116721724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670542
F. Duan, D. Ioannou, W. Jenkins, H. Hughes, M. Liu
Carrier generation by impact ionization in SOI MOSFETs as a function of the strength of channel coupling, adjusted by varying the back gate bias or the silicon film thickness, was extensively studied by extensive PISCES numerical simulations. The results show that stronger front/back channel coupling results in lower carrier generation, and consequently, lower hot carrier degradation. Experimental measurements of the substrate current and hot carrier device degradation verified these results. At the same time, however, the stronger channel coupling results in a lower value for the single-transistor latch-up voltage V/sub DLU/. The above observations mean that there is a trade-off between hot carrier degradation and single transistor latch-up voltage in SOI MOSFETs.
{"title":"Channel coupling imposed tradeoffs on hot carrier degradation and single transistor latch-up in SOI MOSFETs","authors":"F. Duan, D. Ioannou, W. Jenkins, H. Hughes, M. Liu","doi":"10.1109/RELPHY.1998.670542","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670542","url":null,"abstract":"Carrier generation by impact ionization in SOI MOSFETs as a function of the strength of channel coupling, adjusted by varying the back gate bias or the silicon film thickness, was extensively studied by extensive PISCES numerical simulations. The results show that stronger front/back channel coupling results in lower carrier generation, and consequently, lower hot carrier degradation. Experimental measurements of the substrate current and hot carrier device degradation verified these results. At the same time, however, the stronger channel coupling results in a lower value for the single-transistor latch-up voltage V/sub DLU/. The above observations mean that there is a trade-off between hot carrier degradation and single transistor latch-up voltage in SOI MOSFETs.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132225270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：