Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670531
Y. Sambonsugi, T. Sugii
We investigated the HC reliability of deep submicron LDD nMOSFETs with nitride sidewalls, and found a unique stress bias dependence of HC degradation under lower stress bias conditions. This means lifetime estimations are inconclusive because of deviations from the empirical law. Moreover, we succeeded in improving HC reliability in nitride sidewall devices by shifting the location of the HC injection.
{"title":"Hot-carrier degradation mechanism and promising device design of nMOSFETs with nitride sidewall spacer","authors":"Y. Sambonsugi, T. Sugii","doi":"10.1109/RELPHY.1998.670531","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670531","url":null,"abstract":"We investigated the HC reliability of deep submicron LDD nMOSFETs with nitride sidewalls, and found a unique stress bias dependence of HC degradation under lower stress bias conditions. This means lifetime estimations are inconclusive because of deviations from the empirical law. Moreover, we succeeded in improving HC reliability in nitride sidewall devices by shifting the location of the HC injection.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670465
Chun-Ling Chiang, D. T. Hurley
Emission microscopes have over a decade of continuous usage in inspection of semiconductors from the front surface for emission sites. The development of multilevel metallization, flip chip and lead-on-chip (LOC) package design has eliminated or restricted this inspection avenue. Inspection from the backside of semiconductors is complicated by a "silicon filter effect", in both short and long wavelengths, that is tied to the dopant concentration. Based on experience with customer devices of all types and the transmissivity calculation from published optical absorption data, we show that die thinning is a requirement for backside EM analysis. We describe a thinning and polishing technique that enables one to locally thin only the defective die, so that the mechanical integrity of the wafer is preserved to handle probing. We also explore the mechanics of deflection and stress in wafers due to probe needle load in backside wafer-level microprobing, where the wafer is supported only at the edge. We review the development of backside wafer-level microprobing and present the state-of-the-art of this technology. A close examination of the maximum allowable probe needle force leads us to the development of ultra-low-force (ULF) probe cards. We believe that the combination of our local die thinning and polishing technology, ULF probe cards, and fourth-generation emission microscopes, built upon backside wafer microprobers, provides IC failure analysts with a powerful new set of tools in years to come.
{"title":"Dynamics of backside wafer level microprobing","authors":"Chun-Ling Chiang, D. T. Hurley","doi":"10.1109/RELPHY.1998.670465","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670465","url":null,"abstract":"Emission microscopes have over a decade of continuous usage in inspection of semiconductors from the front surface for emission sites. The development of multilevel metallization, flip chip and lead-on-chip (LOC) package design has eliminated or restricted this inspection avenue. Inspection from the backside of semiconductors is complicated by a \"silicon filter effect\", in both short and long wavelengths, that is tied to the dopant concentration. Based on experience with customer devices of all types and the transmissivity calculation from published optical absorption data, we show that die thinning is a requirement for backside EM analysis. We describe a thinning and polishing technique that enables one to locally thin only the defective die, so that the mechanical integrity of the wafer is preserved to handle probing. We also explore the mechanics of deflection and stress in wafers due to probe needle load in backside wafer-level microprobing, where the wafer is supported only at the edge. We review the development of backside wafer-level microprobing and present the state-of-the-art of this technology. A close examination of the maximum allowable probe needle force leads us to the development of ultra-low-force (ULF) probe cards. We believe that the combination of our local die thinning and polishing technology, ULF probe cards, and fourth-generation emission microscopes, built upon backside wafer microprobers, provides IC failure analysts with a powerful new set of tools in years to come.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114459910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670559
H. Shimoe, T. Iijima, T. Iiyama, K. Oyama, H. Taguchi, Y. Hiruta
The reliability of two types of flip chip ball grid array (BGA) was investigated using temperature cycling tests (TCT). It showed that the reliability of the fan-out structure was higher than that of the fan-in structure. The fan-in structure broke more easily at the die edge than the fan-out structure. The highest region of thermal stress on the fan-out structure package was different from that of the fan-in structure package. Therefore, the crack modes were also different. FEM analysis makes the difference of the maximum principal stress on the backside clear. The higher stress region of each structure influences the TCT reliability. The use of a ceramic substrate, as opposed to BT resin, improved the lifetime of the fan-in structure under thermal stress.
{"title":"Influences of fan-in/fan-out structure and underfill fillet on TCT reliability of flip chip BGA","authors":"H. Shimoe, T. Iijima, T. Iiyama, K. Oyama, H. Taguchi, Y. Hiruta","doi":"10.1109/RELPHY.1998.670559","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670559","url":null,"abstract":"The reliability of two types of flip chip ball grid array (BGA) was investigated using temperature cycling tests (TCT). It showed that the reliability of the fan-out structure was higher than that of the fan-in structure. The fan-in structure broke more easily at the die edge than the fan-out structure. The highest region of thermal stress on the fan-out structure package was different from that of the fan-in structure package. Therefore, the crack modes were also different. FEM analysis makes the difference of the maximum principal stress on the backside clear. The higher stress region of each structure influences the TCT reliability. The use of a ceramic substrate, as opposed to BT resin, improved the lifetime of the fan-in structure under thermal stress.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670448
N. A. Dumin
Charge-to-breakdown (Q/sub BD/) is one of the manufacturing parameters that is used as a measure of oxide quality. In this work, the influence of the measurement conditions on Q/sub BD/ is examined, as well as the relationship between Q/sub BD/ and oxide thickness. Using oxides ranging from 45 /spl Aring/ to 80 /spl Aring/, two Q/sub BD/ measurement methods are employed: constant current stress (CCS) and an exponential current ramp (ECR). A variety of current densities (for constant current stress) and step durations (for exponential current ramp) are studied. It is shown that not only does Q/sub BD/ depend on oxide thickness, but that Q/sub BD/ depends strongly on the measurement conditions, and that, depending on the test conditions, Q/sub BD/ can increase or decrease as the oxide thickness decreases. It is also shown that there is a strong agreement between the Q/sub BD/ measured with a constant current stress and the Q/sub BD/ measured with an exponential current ramp. Finally, an algorithm is proposed for transforming the Q/sub BD/ distribution obtained from a series of exponential current ramps into the Q/sub BD/ and/or t/sub BD/ domains of constant current stressing.
{"title":"A new algorithm for transforming exponential current ramp breakdown distributions into constant current TDDB space, and the implications for gate oxide Q/sub BD/ measurement methods","authors":"N. A. Dumin","doi":"10.1109/RELPHY.1998.670448","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670448","url":null,"abstract":"Charge-to-breakdown (Q/sub BD/) is one of the manufacturing parameters that is used as a measure of oxide quality. In this work, the influence of the measurement conditions on Q/sub BD/ is examined, as well as the relationship between Q/sub BD/ and oxide thickness. Using oxides ranging from 45 /spl Aring/ to 80 /spl Aring/, two Q/sub BD/ measurement methods are employed: constant current stress (CCS) and an exponential current ramp (ECR). A variety of current densities (for constant current stress) and step durations (for exponential current ramp) are studied. It is shown that not only does Q/sub BD/ depend on oxide thickness, but that Q/sub BD/ depends strongly on the measurement conditions, and that, depending on the test conditions, Q/sub BD/ can increase or decrease as the oxide thickness decreases. It is also shown that there is a strong agreement between the Q/sub BD/ measured with a constant current stress and the Q/sub BD/ measured with an exponential current ramp. Finally, an algorithm is proposed for transforming the Q/sub BD/ distribution obtained from a series of exponential current ramps into the Q/sub BD/ and/or t/sub BD/ domains of constant current stressing.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670443
S. Kamohara, D. Park, C. Hu
We have successfully developed a new quantitative ITAT (inelastic trap-assisted tunneling) based SILC (stress induced leakage current) model by introducing traps with a deep energy level of around 4.0 eV which can explain two field dependencies, i.e. Fowler-Nordheim (FN) field and the direct tunneling (DT) field dependence. For simple analytical models, we introduce the most favorable trap position, which gives the largest contribution to the leakage current. A-mode and B-mode SILC are the leakage currents in the nominal oxide region and at the weak oxide spots, respectively, which can be deduced by the large difference in the area density between the single trap area (/spl sim/1/spl times/10/sup 11/ cm/sup -2/) and the multi-trap path (/spl sim/1/spl times/10/sup 2/ cm/sup -2/). Our model suggests that for flash EPROM, a 13 nm-oxide thickness is required for 1.0 fC on the floating gate to last 100 years.
{"title":"Deep-trap SILC (stress induced leakage current) model for nominal and weak oxides","authors":"S. Kamohara, D. Park, C. Hu","doi":"10.1109/RELPHY.1998.670443","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670443","url":null,"abstract":"We have successfully developed a new quantitative ITAT (inelastic trap-assisted tunneling) based SILC (stress induced leakage current) model by introducing traps with a deep energy level of around 4.0 eV which can explain two field dependencies, i.e. Fowler-Nordheim (FN) field and the direct tunneling (DT) field dependence. For simple analytical models, we introduce the most favorable trap position, which gives the largest contribution to the leakage current. A-mode and B-mode SILC are the leakage currents in the nominal oxide region and at the weak oxide spots, respectively, which can be deduced by the large difference in the area density between the single trap area (/spl sim/1/spl times/10/sup 11/ cm/sup -2/) and the multi-trap path (/spl sim/1/spl times/10/sup 2/ cm/sup -2/). Our model suggests that for flash EPROM, a 13 nm-oxide thickness is required for 1.0 fC on the floating gate to last 100 years.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121416033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670473
S. Bothra, H. Sur, V. Liang
The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.
{"title":"A new failure mechanism by corrosion of tungsten in a tungsten plug process","authors":"S. Bothra, H. Sur, V. Liang","doi":"10.1109/RELPHY.1998.670473","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670473","url":null,"abstract":"The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132048636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670670
K. Goto, J. Watanabe, T. Sukegawa, A. Fushida, T. Sakuma, T. Sugii
We investigated the leakage mechanisms of both Co and Ni salicide processes. Statistical analyses of the junction leakage and a direct light observation of the leakage points from Co and Ni salicided junctions revealed that Ni salicide also shows many localized spots that cause leakage just like those in the Co salicide case, but in the Ni salicide case, the spots are along the LOCOS edge. Leakage currents were successfully simulated by means of a new spike-leakage model that considers both area and peripheral dependent spike leakage. To explain the subsequent results, we proposed a stress induced spike growth model. Working from this model, we developed a spike-leakage-free Co salicide process using a Ge pre-amorphization step.
{"title":"A comparative study of leakage mechanism of Co and Ni salicide processes","authors":"K. Goto, J. Watanabe, T. Sukegawa, A. Fushida, T. Sakuma, T. Sugii","doi":"10.1109/RELPHY.1998.670670","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670670","url":null,"abstract":"We investigated the leakage mechanisms of both Co and Ni salicide processes. Statistical analyses of the junction leakage and a direct light observation of the leakage points from Co and Ni salicided junctions revealed that Ni salicide also shows many localized spots that cause leakage just like those in the Co salicide case, but in the Ni salicide case, the spots are along the LOCOS edge. Leakage currents were successfully simulated by means of a new spike-leakage model that considers both area and peripheral dependent spike leakage. To explain the subsequent results, we proposed a stress induced spike growth model. Working from this model, we developed a spike-leakage-free Co salicide process using a Ge pre-amorphization step.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132225439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670668
E.M. Atakov, T. Sriram, D. Dunnell, S. Pizzanello
We characterized the reliability of multiple-via contacts, as well as the impact of the contact current direction on the failure statistics and short-length effects in Ti-Al(Cu)-Ti-TiN lines. A significant difference between the sheet resistances of the top and bottom shunting layers results in a bimodal failure time distribution for the downward electron flow direction. It also causes a significant difference in the short-length resistance saturation for the two current directions.
{"title":"Effect of VLSI interconnect layout on electromigration performance","authors":"E.M. Atakov, T. Sriram, D. Dunnell, S. Pizzanello","doi":"10.1109/RELPHY.1998.670668","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670668","url":null,"abstract":"We characterized the reliability of multiple-via contacts, as well as the impact of the contact current direction on the failure statistics and short-length effects in Ti-Al(Cu)-Ti-TiN lines. A significant difference between the sheet resistances of the top and bottom shunting layers results in a bimodal failure time distribution for the downward electron flow direction. It also causes a significant difference in the short-length resistance saturation for the two current directions.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132448375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670441
J. McPherson, H. Mogul
A temperature-independent field acceleration parameter /spl gamma/ and a field-independent activation energy /spl Delta/Ho can result when different types of disturbed bonding states are mixed during time-dependent dielectric breakdown (TDDB) testing of SiO/sub 2/ thin films. While /spl gamma/ for each defect type alone has the expected 1/T dependence and /spl Delta/Ho shows a linear decrease with electric field, a nearly temperature-independent /spl gamma/ and a field-independent /spl Delta/Ho can result when two or more disturbed bonding states are mixed. These observations suggest strongly that the oxygen vacancy is an important intrinsic defect for breakdown and that field, not current, is the cause of TDDB under low-field conditions.
{"title":"Disturbed bonding states in SiO/sub 2/ thin-films and their impact on time-dependent dielectric breakdown","authors":"J. McPherson, H. Mogul","doi":"10.1109/RELPHY.1998.670441","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670441","url":null,"abstract":"A temperature-independent field acceleration parameter /spl gamma/ and a field-independent activation energy /spl Delta/Ho can result when different types of disturbed bonding states are mixed during time-dependent dielectric breakdown (TDDB) testing of SiO/sub 2/ thin films. While /spl gamma/ for each defect type alone has the expected 1/T dependence and /spl Delta/Ho shows a linear decrease with electric field, a nearly temperature-independent /spl gamma/ and a field-independent /spl Delta/Ho can result when two or more disturbed bonding states are mixed. These observations suggest strongly that the oxygen vacancy is an important intrinsic defect for breakdown and that field, not current, is the cause of TDDB under low-field conditions.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114771673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670561
M. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, W. Craig
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.
{"title":"Latchup in CMOS technology","authors":"M. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, W. Craig","doi":"10.1109/RELPHY.1998.670561","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670561","url":null,"abstract":"This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128944884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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