Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670555
M. Saran, R. Cox, C. Martin, G. Ryan, T. Kudoh, M. Kanasugi, J. Hortaleza, M. Ibnabdeljalil, M. Murtuza, D. Capistrano, R. Roderos, R. Macaraeg
A new bond failure mechanism related to the new, mechanically weak, low-k dielectrics in intermetal dielectric stacks is presented. Mechanical reinforcement of the dielectric stack through the use of metal grids is demonstrated to be effective to prevent this damage. Possible failure mechanisms are discussed.
{"title":"Elimination of bond-pad damage through structural reinforcement of intermetal dielectrics","authors":"M. Saran, R. Cox, C. Martin, G. Ryan, T. Kudoh, M. Kanasugi, J. Hortaleza, M. Ibnabdeljalil, M. Murtuza, D. Capistrano, R. Roderos, R. Macaraeg","doi":"10.1109/RELPHY.1998.670555","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670555","url":null,"abstract":"A new bond failure mechanism related to the new, mechanically weak, low-k dielectrics in intermetal dielectric stacks is presented. Mechanical reinforcement of the dielectric stack through the use of metal grids is demonstrated to be effective to prevent this damage. Possible failure mechanisms are discussed.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670446
Y. Wu, G. Lucovsky, H. Z. Massoud
Dual layer dielectrics have been formed by remote PECVD of ultra-thin (0.4/spl sim/1.2 nm) nitrides on thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p/sup +/ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal for 1/spl sim/4 minutes at 1000/spl deg/C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C-V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q/sub bd/ value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However, there were essentially no differences in the mid-gap interface state densities, D/sub it/, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p/sup +/ poly-Si gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.
{"title":"Improvement of gate dielectric reliability for p/sup +/ poly MOS devices using remote PECVD top nitride deposition on thin gate oxides","authors":"Y. Wu, G. Lucovsky, H. Z. Massoud","doi":"10.1109/RELPHY.1998.670446","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670446","url":null,"abstract":"Dual layer dielectrics have been formed by remote PECVD of ultra-thin (0.4/spl sim/1.2 nm) nitrides on thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p/sup +/ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal for 1/spl sim/4 minutes at 1000/spl deg/C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C-V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q/sub bd/ value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However, there were essentially no differences in the mid-gap interface state densities, D/sub it/, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p/sup +/ poly-Si gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115965931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670450
M. Borgarino, R. Plana, S. Delage, H. Blanck, F. Fantini, J. Graffeuil
This paper reports on the early variations of the base current (burn-in effect) in SiN passivated, double-mesa processed, In/C-doped GaInP-GaAs HBTs induced by stressing the devices at room temperature and under different bias conditions. The investigation was carried out by means of DC measurements and low frequency noise analysis, in the 250 Hz-100 kHz frequency range. The results demonstrated that the burn-in effect is due to a reduction of surface recombination currents in the extrinsic base region around the emitter perimeter. This reduction in surface recombination current is attributed to the passivation of defects at the passivation/semiconductor interface by hydrogen atoms debonded from C-H complexes in the base layer during the stress.
{"title":"Early variations of the base current in In/C-doped GaInP-GaAs HBTs","authors":"M. Borgarino, R. Plana, S. Delage, H. Blanck, F. Fantini, J. Graffeuil","doi":"10.1109/RELPHY.1998.670450","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670450","url":null,"abstract":"This paper reports on the early variations of the base current (burn-in effect) in SiN passivated, double-mesa processed, In/C-doped GaInP-GaAs HBTs induced by stressing the devices at room temperature and under different bias conditions. The investigation was carried out by means of DC measurements and low frequency noise analysis, in the 250 Hz-100 kHz frequency range. The results demonstrated that the burn-in effect is due to a reduction of surface recombination currents in the extrinsic base region around the emitter perimeter. This reduction in surface recombination current is attributed to the passivation of defects at the passivation/semiconductor interface by hydrogen atoms debonded from C-H complexes in the base layer during the stress.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121631906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670435
J. England, R. England
Nowhere is the pace of change so rapid or so dramatic as in the semiconductor industry. For any industry to sustain 15% growth per year over a 40-year period is remarkable, but in the next few years, that growth rate is expected to accelerate, creating an industry that rivals historically dominant industries such as automotive and steel for a share of the global economy. Moore's Law has proven remarkably successful in characterizing the growth of the semiconductor industry for the past three decades. During that period, the core microelectronic materials-silicon substrate, SiO/sub 2/-based dielectrics, and aluminum metallization-have undergone relatively minor perturbations. Now, however, a discontinuity in basic semiconductor materials will be necessary for the industry to continue on the curve described by Moore's Law. The materials on which careers have been based are giving way to new gate and interlevel dielectrics, and copper metallization is replacing aluminum-alloy metallization. Given the size of our industry and its impact on the global economy, an accelerated understanding of the reliability physics of these new materials is essential. This paper deals with the work environment, skills and methods required for the reliability scientist to prepare the semiconductor industry for the new millennium.
{"title":"The reliability challenge: New materials in the new millennium. Moore's Law drives a discontinuity","authors":"J. England, R. England","doi":"10.1109/RELPHY.1998.670435","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670435","url":null,"abstract":"Nowhere is the pace of change so rapid or so dramatic as in the semiconductor industry. For any industry to sustain 15% growth per year over a 40-year period is remarkable, but in the next few years, that growth rate is expected to accelerate, creating an industry that rivals historically dominant industries such as automotive and steel for a share of the global economy. Moore's Law has proven remarkably successful in characterizing the growth of the semiconductor industry for the past three decades. During that period, the core microelectronic materials-silicon substrate, SiO/sub 2/-based dielectrics, and aluminum metallization-have undergone relatively minor perturbations. Now, however, a discontinuity in basic semiconductor materials will be necessary for the industry to continue on the curve described by Moore's Law. The materials on which careers have been based are giving way to new gate and interlevel dielectrics, and copper metallization is replacing aluminum-alloy metallization. Given the size of our industry and its impact on the global economy, an accelerated understanding of the reliability physics of these new materials is essential. This paper deals with the work environment, skills and methods required for the reliability scientist to prepare the semiconductor industry for the new millennium.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124519549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670460
D. Barton, M. Osiński, P. Perlin, P. Eliseev, J. Lee
We performed a degradation study of high-brightness Nichia single-quantum well AlGaN-InGaN-GaN green light-emitting diodes (LEDs). The devices were subjected to high current electrical stress with current pulse amplitudes between 1 A and 7 A and voltages between 10 V and 70 V with a pulse length of 100 ns and a 1 kHz repetition rate. The study showed that when the current amplitude was increased above 6 A, a fast (about 1 s) degradation occurred, with a visible discharge between the p- and n-type electrodes. Subsequent failure analysis revealed severe damage to the metal contacts which lead to the formation of shorts in the surface plane of the diode. For currents smaller than 6 A, a slow degradation was observed as a decrease in optical power and an increase in the reverse current leakage. After between 24 and 100 hours however, a rapid degradation occurred which was similar to the rapid degradation observed at higher currents. The failure analysis results indicate that the degradation process begins with carbonization of the plastic encapsulation material on the diode surface, which leads to the formation of a conductive path across the LED and subsequently to the destruction of the diode itself.
{"title":"Degradation of single-quantum well InGaN green light emitting diodes under high electrical stress","authors":"D. Barton, M. Osiński, P. Perlin, P. Eliseev, J. Lee","doi":"10.1109/RELPHY.1998.670460","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670460","url":null,"abstract":"We performed a degradation study of high-brightness Nichia single-quantum well AlGaN-InGaN-GaN green light-emitting diodes (LEDs). The devices were subjected to high current electrical stress with current pulse amplitudes between 1 A and 7 A and voltages between 10 V and 70 V with a pulse length of 100 ns and a 1 kHz repetition rate. The study showed that when the current amplitude was increased above 6 A, a fast (about 1 s) degradation occurred, with a visible discharge between the p- and n-type electrodes. Subsequent failure analysis revealed severe damage to the metal contacts which lead to the formation of shorts in the surface plane of the diode. For currents smaller than 6 A, a slow degradation was observed as a decrease in optical power and an increase in the reverse current leakage. After between 24 and 100 hours however, a rapid degradation occurred which was similar to the rapid degradation observed at higher currents. The failure analysis results indicate that the degradation process begins with carbonization of the plastic encapsulation material on the diode surface, which leads to the formation of a conductive path across the LED and subsequently to the destruction of the diode itself.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121340634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670556
E.M. Philofsky, C. Ostrander, S. J. Hartman
Degraded performance and reduced yields of semiconductor devices have been attributed to gaseous microcontamination during wafer processing. In particular, hydrogen contamination can degrade the performance of both Si and GaAs-based devices. Hydrogen is therefore maintained at concentrations below 10 ppb (parts-per-billion) in all UHP gases supplied to process tools. When compared to wafer processing, microcontamination-related yield losses during back-end processing are relatively unknown. Plastic packaging assembly is one of the more likely back-end processes leading to yield loss based on the elevated temperature and chemical exposure of the die during molding. Such yield losses are known to occur in the manufacture of ferroelectric memory devices and have potentially been attributed to: (1) thermal budget, (2) stress, and (3) thin film reduction by hydrogen. Thermal bakes at temperatures below the Curie point degrade the ferroelectric capacitor as a result of relaxation and aging. Stress from the assembly and molding process can also degrade the capacitors by altering the tetragonality of the perovskite lattice. Hydrogen can chemically reduce the ferroelectric film and destroy the adhesion between the ferroelectric and the electrode. This study focuses on determining the hydrogen evolved from plastic packaging materials during molding and past mold cure and its effect on the yield and retention reliability of ferroelectric memory devices.
{"title":"The evolution of hydrogen from plastic molding compound and it's effect on the yield and reliability of ferroelectric memories","authors":"E.M. Philofsky, C. Ostrander, S. J. Hartman","doi":"10.1109/RELPHY.1998.670556","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670556","url":null,"abstract":"Degraded performance and reduced yields of semiconductor devices have been attributed to gaseous microcontamination during wafer processing. In particular, hydrogen contamination can degrade the performance of both Si and GaAs-based devices. Hydrogen is therefore maintained at concentrations below 10 ppb (parts-per-billion) in all UHP gases supplied to process tools. When compared to wafer processing, microcontamination-related yield losses during back-end processing are relatively unknown. Plastic packaging assembly is one of the more likely back-end processes leading to yield loss based on the elevated temperature and chemical exposure of the die during molding. Such yield losses are known to occur in the manufacture of ferroelectric memory devices and have potentially been attributed to: (1) thermal budget, (2) stress, and (3) thin film reduction by hydrogen. Thermal bakes at temperatures below the Curie point degrade the ferroelectric capacitor as a result of relaxation and aging. Stress from the assembly and molding process can also degrade the capacitors by altering the tetragonality of the perovskite lattice. Hydrogen can chemically reduce the ferroelectric film and destroy the adhesion between the ferroelectric and the electrode. This study focuses on determining the hydrogen evolved from plastic packaging materials during molding and past mold cure and its effect on the yield and retention reliability of ferroelectric memory devices.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670539
A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, M. Foisy
Halo implants with various tilt angles and energies were compared from the point of hot carrier reliability. Our study shows that a larger tilt or a deeper, more energetic halo implant leads to stronger reverse short channel effects and higher electric field in the extension/channel junction. However, the net impact of a sharper extension/channel junction on hot carrier degradation was found to be minimal, because the weaker halo devices have higher substrate current resulting from higher drain currents which counterbalances increased electric field in the extension-channel junction for the stronger halo devices. However, when devices from two lots with similar performance parametrics, such as similar threshold voltage (V/sub t/) roll-off, were compared, larger tilt/lower energy halo devices were found to have less degradation than lower tilt/higher energy halos.
{"title":"Effects of halo implant on hot carrier reliability of sub-quarter micron MOSFETs","authors":"A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, M. Foisy","doi":"10.1109/RELPHY.1998.670539","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670539","url":null,"abstract":"Halo implants with various tilt angles and energies were compared from the point of hot carrier reliability. Our study shows that a larger tilt or a deeper, more energetic halo implant leads to stronger reverse short channel effects and higher electric field in the extension/channel junction. However, the net impact of a sharper extension/channel junction on hot carrier degradation was found to be minimal, because the weaker halo devices have higher substrate current resulting from higher drain currents which counterbalances increased electric field in the extension-channel junction for the stronger halo devices. However, when devices from two lots with similar performance parametrics, such as similar threshold voltage (V/sub t/) roll-off, were compared, larger tilt/lower energy halo devices were found to have less degradation than lower tilt/higher energy halos.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124352608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670560
M. Amagai
A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behaviour of the solder joints in chip scale packages (CSP) mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. Finite element models, incorporating the viscoplastic flow and evolution equations, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless lead-on-chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints, while a dwell time in excess of 10 minutes per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated, and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.
{"title":"Chip scale package (CSP) solder joint reliability and modeling","authors":"M. Amagai","doi":"10.1109/RELPHY.1998.670560","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670560","url":null,"abstract":"A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behaviour of the solder joints in chip scale packages (CSP) mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. Finite element models, incorporating the viscoplastic flow and evolution equations, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless lead-on-chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints, while a dwell time in excess of 10 minutes per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated, and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670545
S. Renn, C. Raynaud, J. Pelloie, F. Balestra
A thorough investigation on hot-carrier effects in deep submicron N- and P-channel SOI MOSFETs is reported in this paper. The following studies are presented in order to thoroughly assess the reliability of SOI technologies: (i) comparison of hot-carrier effects in SIMOX and Unibond MOSFETs; (ii) evaluation of the hot-carrier immunity of fully and partially depleted devices; (iii) analysis of the degradation in N- and P-channel transistors; and (iv) investigation of the aging/recovery mechanisms.
{"title":"Comparison of hot-carrier effects in deep submicron N- and P-channel partially- and fully-depleted Unibond and SIMOX MOSFETs","authors":"S. Renn, C. Raynaud, J. Pelloie, F. Balestra","doi":"10.1109/RELPHY.1998.670545","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670545","url":null,"abstract":"A thorough investigation on hot-carrier effects in deep submicron N- and P-channel SOI MOSFETs is reported in this paper. The following studies are presented in order to thoroughly assess the reliability of SOI technologies: (i) comparison of hot-carrier effects in SIMOX and Unibond MOSFETs; (ii) evaluation of the hot-carrier immunity of fully and partially depleted devices; (iii) analysis of the degradation in N- and P-channel transistors; and (iv) investigation of the aging/recovery mechanisms.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122798228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1998.670552
Tahui Wang, C. Hsu, L. Chiang, N. Zous, T. Chao, C. Chang
Drain leakage current degradation at zero V/sub gs/ in a hot carrier stressed n-MOSFET is measured and modeled. The dependences of drain leakage current on supply voltage and temperature are characterized. In modeling, various drain leakage current mechanisms including drain-to-source subthreshold leakage current, band-to-band tunneling current and interface trap assisted leakage current are taken into account. The results show that interface trap induced leakage current appears to be a dominant drain leakage mechanism as the supply voltage is scaled below 3.0 V. Drain leakage current degradation by orders of magnitude has been observed due to hot carrier stress.
{"title":"Voltage scaling and temperature effects on drain leakage current degradation in a hot carrier stressed n-MOSFET","authors":"Tahui Wang, C. Hsu, L. Chiang, N. Zous, T. Chao, C. Chang","doi":"10.1109/RELPHY.1998.670552","DOIUrl":"https://doi.org/10.1109/RELPHY.1998.670552","url":null,"abstract":"Drain leakage current degradation at zero V/sub gs/ in a hot carrier stressed n-MOSFET is measured and modeled. The dependences of drain leakage current on supply voltage and temperature are characterized. In modeling, various drain leakage current mechanisms including drain-to-source subthreshold leakage current, band-to-band tunneling current and interface trap assisted leakage current are taken into account. The results show that interface trap induced leakage current appears to be a dominant drain leakage mechanism as the supply voltage is scaled below 3.0 V. Drain leakage current degradation by orders of magnitude has been observed due to hot carrier stress.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"1999 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128256082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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