Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644500
K. Kakushima, R. Yoshihara, K. Tsutsui, H. Iwai
With continuous demands for high performance and low power consumption CMOS devices, high mobility channel materials have been investigated for future end-of-roadmap electronic devices [1]. Among high mobility semiconductors, Ge channel have been focused as a strong candidate for both n- and p-type channel devices owing to high electron and hole mobility. To benefit the high channel mobility, low resistivity Ohmic contacts are essential for source and drain regions [2]. Commonly, an intuitive approach to achieve low Ohmic contact is to adopt heavily doped source and drain junctions, so as to increase the tunneling probability at metal/semiconductor interfaces. However, doping for Ge substrate suffer from poor solubility of dopants, large diffusion coefficient, incomplete activation of dopants [3]. Also, a strong Fermi-level pinning near the valence band of Ge results in large Schottky barrier height for electrons, which eventually leads to high contact resistance for n-type Ge channel [4]. This work presents a novel approach to obtain Ohmic characteristics with low temperature process on n-type Ge substrate without ion implantation.
{"title":"A low temperature Ohmic contact process for n-type Ge substrates","authors":"K. Kakushima, R. Yoshihara, K. Tsutsui, H. Iwai","doi":"10.1109/IWJT.2013.6644500","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644500","url":null,"abstract":"With continuous demands for high performance and low power consumption CMOS devices, high mobility channel materials have been investigated for future end-of-roadmap electronic devices [1]. Among high mobility semiconductors, Ge channel have been focused as a strong candidate for both n- and p-type channel devices owing to high electron and hole mobility. To benefit the high channel mobility, low resistivity Ohmic contacts are essential for source and drain regions [2]. Commonly, an intuitive approach to achieve low Ohmic contact is to adopt heavily doped source and drain junctions, so as to increase the tunneling probability at metal/semiconductor interfaces. However, doping for Ge substrate suffer from poor solubility of dopants, large diffusion coefficient, incomplete activation of dopants [3]. Also, a strong Fermi-level pinning near the valence band of Ge results in large Schottky barrier height for electrons, which eventually leads to high contact resistance for n-type Ge channel [4]. This work presents a novel approach to obtain Ohmic characteristics with low temperature process on n-type Ge substrate without ion implantation.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132571856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644491
S. Deleonibus, F. Andrieu, P. Batude, X. Jehl, F. Martin, F. Milési, S. Morvan, F. Nemouchi, M. Sanquer, M. Vinet
Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.
{"title":"Future micro/nano-electronics: Towards full 3D and zero variability","authors":"S. Deleonibus, F. Andrieu, P. Batude, X. Jehl, F. Martin, F. Milési, S. Morvan, F. Nemouchi, M. Sanquer, M. Vinet","doi":"10.1109/IWJT.2013.6644491","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644491","url":null,"abstract":"Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122363571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644511
M. Current, Yao-Jen Lee, Yu-Lun Lu, Ta-Chun Cho, T. Chao, H. Onoda, K. Sekar, N. Tokoro
Effects of microwave (MWA) at ≈500 C and rapid-thermal annealing at 600 to 1000 C are compared for phosphorous-doped, strained Si(100) and (110) implanted with molecular Carbon (C7H7) ions. Substitutional Carbon levels at 1.44% were achieved for P-doped, C7 implanted strained nMOS S/D type junctions with MWA.
{"title":"Microwave and RTA annealing of phos-doped, strained Si(100) and (110) implanted with molecular Carbon ions","authors":"M. Current, Yao-Jen Lee, Yu-Lun Lu, Ta-Chun Cho, T. Chao, H. Onoda, K. Sekar, N. Tokoro","doi":"10.1109/IWJT.2013.6644511","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644511","url":null,"abstract":"Effects of microwave (MWA) at ≈500 C and rapid-thermal annealing at 600 to 1000 C are compared for phosphorous-doped, strained Si(100) and (110) implanted with molecular Carbon (C7H7) ions. Substitutional Carbon levels at 1.44% were achieved for P-doped, C7 implanted strained nMOS S/D type junctions with MWA.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115981581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644505
G. Majumdar
Summary form only given. The role of power electronics and power devices in addressing the challenges in power and energy conversions and storage have continuously been very important and have been given wide attention also due to the fact that energy issues arising from climate change has risen to be a crucial global issue. In power electronic applications, the power density factor related to system designs has improved remarkably in the past two decades. The main contributions in this growth have come from timely development of newer power modules achieved through multi-dimensional major breakthroughs in IGBT and other power chip technologies, packaging structures and functionality integration concepts. Driven by various application needs in the past decades, various generations of power modules have evolved so far and have been widely applied in different power electronics equipment covering industrial motor controls, house-hold appliances, railway traction automotive power-train electronics, windmill and solar power generation systems etc. Today, power devices have become an extremely important component group for its role to sustain growth of power electronics and, thus, to contribute effectively in the current global effort to curb climate change. Under such backgrounds, this presentation is prepared to explain various state-of-the-art power device technologies focusing on IGBT modules and IPMs. It will also include highlights of future technological trends in such fields including prospects of SiC devices. Fig. 1 and 2 provide a summary of the presentation.
{"title":"Advanced power semiconductor technologies for efficient energy conversion","authors":"G. Majumdar","doi":"10.1109/IWJT.2013.6644505","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644505","url":null,"abstract":"Summary form only given. The role of power electronics and power devices in addressing the challenges in power and energy conversions and storage have continuously been very important and have been given wide attention also due to the fact that energy issues arising from climate change has risen to be a crucial global issue. In power electronic applications, the power density factor related to system designs has improved remarkably in the past two decades. The main contributions in this growth have come from timely development of newer power modules achieved through multi-dimensional major breakthroughs in IGBT and other power chip technologies, packaging structures and functionality integration concepts. Driven by various application needs in the past decades, various generations of power modules have evolved so far and have been widely applied in different power electronics equipment covering industrial motor controls, house-hold appliances, railway traction automotive power-train electronics, windmill and solar power generation systems etc. Today, power devices have become an extremely important component group for its role to sustain growth of power electronics and, thus, to contribute effectively in the current global effort to curb climate change. Under such backgrounds, this presentation is prepared to explain various state-of-the-art power device technologies focusing on IGBT modules and IPMs. It will also include highlights of future technological trends in such fields including prospects of SiC devices. Fig. 1 and 2 provide a summary of the presentation.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126881028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644498
I. Mizushima, T. Sadoh, M. Miyao
Single-crystal Ge layers on insulating films (GOI) are desired to achieve advanced 3-dimensional large-scale integrated circuits and high-performance thin-film transistors. Rapid-melting Ge growth seeded from Si substrates, which utilizes rapid thermal annealing (RTA) technique with narrow Ge stripes on insulator, achieves chip-scale (~cm length) GOI structures with (100), (110), and (111) orientations. Profile of Si in Ge stripe is robustly controlled by sample structures (stripe length) and process conditions (cooling rate).
{"title":"Formation of Ge-on-Insulator Structures on Si platform by SiGe-mixing-triggered rapid-melting growth using RTA technique","authors":"I. Mizushima, T. Sadoh, M. Miyao","doi":"10.1109/IWJT.2013.6644498","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644498","url":null,"abstract":"Single-crystal Ge layers on insulating films (GOI) are desired to achieve advanced 3-dimensional large-scale integrated circuits and high-performance thin-film transistors. Rapid-melting Ge growth seeded from Si substrates, which utilizes rapid thermal annealing (RTA) technique with narrow Ge stripes on insulator, achieves chip-scale (~cm length) GOI structures with (100), (110), and (111) orientations. Profile of Si in Ge stripe is robustly controlled by sample structures (stripe length) and process conditions (cooling rate).","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644514
Yi Zhao, Wangran Wu, Jiabao Sun, Yi Shi
In this paper, we review the recent progresses about the effect of the uniaxial tensile strain on the electrical properties of the Si p-n junctions and MOS capacitors. We found that the uniaxial tensile stress could increase the junction current in the large-forward-bias region significantly. However, only a slight current increase has been observed in the diffusion-current-dominant region. In nMOSFETs the uniaxial tensile strain could enhance Isub significantly, while decreasing Ig slightly. Furthermore, in pMOSFETs, the uniaxial tensile strain could enhance both Ig and Isub. All these results have been explained by taking the strain induced subband structure modulation, current components variation and the piezoresistance effect into consideration.
{"title":"Strain-induced I-V characteristics modulation of p-n junctions and MOS capacitors in Si CMOS devices","authors":"Yi Zhao, Wangran Wu, Jiabao Sun, Yi Shi","doi":"10.1109/IWJT.2013.6644514","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644514","url":null,"abstract":"In this paper, we review the recent progresses about the effect of the uniaxial tensile strain on the electrical properties of the Si p-n junctions and MOS capacitors. We found that the uniaxial tensile stress could increase the junction current in the large-forward-bias region significantly. However, only a slight current increase has been observed in the diffusion-current-dominant region. In nMOSFETs the uniaxial tensile strain could enhance Isub significantly, while decreasing Ig slightly. Furthermore, in pMOSFETs, the uniaxial tensile strain could enhance both Ig and Isub. All these results have been explained by taking the strain induced subband structure modulation, current components variation and the piezoresistance effect into consideration.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644516
Keping Han, P. Hsu, Matthew Beach, T. Henry, N. Yoshida, A. Brand
FinFET has emerged as a device structure to enable the device scaling at and beyond the 22nm technology node due to increasingly stringent demands for maximum device speed, lower leakage current and control of random dopant fluctuation effects. High-k dielectric (Hik)/metal gate (MG) technology makes it feasible to obtain improved Effective Oxide Thickness (EOT) scaling and reduced leakage. Replacement metal gate (RMG) flows have been used for high performance logic volume production at and beyond 45nm node [1]. Precise threshold voltage (Vt) control and multiple Vt are required for FinFET device architectures for future devices. This paper proposes an ion implantation approach for modulating metal gate work function for both n-metal and p-metal gate used in a HiK last and replacement gate process. This approach offers simplified integration flow where no additional mask is needed and resist mask can be used. The effective work function (eWF) was measured along with the EOT and Gate Leakage (Jg). Stress Induced Leakage Current (SILC) method was used for testing HiK stack reliability. The results showed up to 200mV eWF modulation by ion implantation with fine control and without EOT and Jg degradation. The effect of implant species and dose on the eWF was studied in this paper. SIMS analysis of HKMG stack on the blanket wafer was used to determine the dopant distribution and explore the possible mechanism for metal gate work function modulation by ion implantation.
{"title":"Metal gate work function modulation by ion implantation for multiple threshold voltage FinFET devices","authors":"Keping Han, P. Hsu, Matthew Beach, T. Henry, N. Yoshida, A. Brand","doi":"10.1109/IWJT.2013.6644516","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644516","url":null,"abstract":"FinFET has emerged as a device structure to enable the device scaling at and beyond the 22nm technology node due to increasingly stringent demands for maximum device speed, lower leakage current and control of random dopant fluctuation effects. High-k dielectric (Hik)/metal gate (MG) technology makes it feasible to obtain improved Effective Oxide Thickness (EOT) scaling and reduced leakage. Replacement metal gate (RMG) flows have been used for high performance logic volume production at and beyond 45nm node [1]. Precise threshold voltage (Vt) control and multiple Vt are required for FinFET device architectures for future devices. This paper proposes an ion implantation approach for modulating metal gate work function for both n-metal and p-metal gate used in a HiK last and replacement gate process. This approach offers simplified integration flow where no additional mask is needed and resist mask can be used. The effective work function (eWF) was measured along with the EOT and Gate Leakage (Jg). Stress Induced Leakage Current (SILC) method was used for testing HiK stack reliability. The results showed up to 200mV eWF modulation by ion implantation with fine control and without EOT and Jg degradation. The effect of implant species and dose on the eWF was studied in this paper. SIMS analysis of HKMG stack on the blanket wafer was used to determine the dopant distribution and explore the possible mechanism for metal gate work function modulation by ion implantation.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644499
Ming-Kun Huang, Wen-Fa Wu, C. Shih, Shen-Li Chen
This work investigates the formation of arsenic segregated Ytterbium and Nickel silicide using low-temperature microwave annealing. Two types of dopant segregation approaches, implant-before-silicidation and implantation-through-metal, are performed to examine the electrical properties of the microwave annealed silicide. Results of current-voltage curves and dopant distribution profiles are compared with those using rapid thermal annealing.
{"title":"Formation of arsenic segregated Ytterbium and Nickel silicide using microwave annealing","authors":"Ming-Kun Huang, Wen-Fa Wu, C. Shih, Shen-Li Chen","doi":"10.1109/IWJT.2013.6644499","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644499","url":null,"abstract":"This work investigates the formation of arsenic segregated Ytterbium and Nickel silicide using low-temperature microwave annealing. Two types of dopant segregation approaches, implant-before-silicidation and implantation-through-metal, are performed to examine the electrical properties of the microwave annealed silicide. Results of current-voltage curves and dopant distribution profiles are compared with those using rapid thermal annealing.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133103439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644513
P. Xu, Xiangbiao Zhou, Na Zhao, Dan Zhao, Dongping Wu
Microwave annealing was used for the activation of both n-and p-type ultra-shallow junctions, formed by pre-amorphization Ge implant followed by low energy n-and p-type dopant implant. The regrowth of a-Si layer was completed after 50 seconds microwave annealing. However, the EOR defects were still clearly visible even after 1200 seconds annealing. The maximum fraction of hall electrical activation was 29.1% for BF2-implanted samples and 79.4% for As-implanted ones. Dopant deactivation occurred when the annealing time was longer than 100 seconds.
{"title":"Formation of ultra-shallow junctions with pre-amorphization implant and microwave annealing","authors":"P. Xu, Xiangbiao Zhou, Na Zhao, Dan Zhao, Dongping Wu","doi":"10.1109/IWJT.2013.6644513","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644513","url":null,"abstract":"Microwave annealing was used for the activation of both n-and p-type ultra-shallow junctions, formed by pre-amorphization Ge implant followed by low energy n-and p-type dopant implant. The regrowth of a-Si layer was completed after 50 seconds microwave annealing. However, the EOR defects were still clearly visible even after 1200 seconds annealing. The maximum fraction of hall electrical activation was 29.1% for BF2-implanted samples and 79.4% for As-implanted ones. Dopant deactivation occurred when the annealing time was longer than 100 seconds.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123635400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-06DOI: 10.1109/IWJT.2013.6644501
S. Jian, C. Jeng, Ting-Chun Wang, Chih-Mu Huang, Ying-Lang Wang, H. Nishigaki, N. Hasuike, H. Harima, W. Yoo
Plasma processes have long been used in various stages of semiconductor device fabrication. Plasma enhanced chemical vapor deposition (PECVD) has been widely used as a low temperature silicon dioxide film deposition method in the semiconductor industry. [1,2] Various modes of plasma etching techniques also have been playing major roles in the silicon industry. Physical vapor deposition (PVD or sputtering), ion implantation, plasma ashing and plasma doping (PD) are a few examples of widely adapted plasma process techniques.
{"title":"Photoluminescence and Raman characterization of excessive plasma etch damage of silicon","authors":"S. Jian, C. Jeng, Ting-Chun Wang, Chih-Mu Huang, Ying-Lang Wang, H. Nishigaki, N. Hasuike, H. Harima, W. Yoo","doi":"10.1109/IWJT.2013.6644501","DOIUrl":"https://doi.org/10.1109/IWJT.2013.6644501","url":null,"abstract":"Plasma processes have long been used in various stages of semiconductor device fabrication. Plasma enhanced chemical vapor deposition (PECVD) has been widely used as a low temperature silicon dioxide film deposition method in the semiconductor industry. [1,2] Various modes of plasma etching techniques also have been playing major roles in the silicon industry. Physical vapor deposition (PVD or sputtering), ion implantation, plasma ashing and plasma doping (PD) are a few examples of widely adapted plasma process techniques.","PeriodicalId":196705,"journal":{"name":"2013 13th International Workshop on Junction Technology (IWJT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124563818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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