Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351672
Bumhee Bae, Jonghyun Cho, Joungho Kim
In this paper, we propose the on-chip design techniques for controlling Power Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps for explaining the proposed design technique. First, we explain what the PSN coupling path is on ADC. The PSN will couple from noise source to noise victim via power distribution network and circuit path. Second, we propose how we can reduce the noise coupling effects. The comparator is essential circuit to ADC and most sensitive circuit to PSN in ADC. Therefore, it is important to reduce the noise coupling effects on comparator for designing ADC which is non-sensitive to PSN. The comparator has two input nodes, and the differential voltage between two input nodes affect to ADC output. The impedance imbalance between two comparator inputs is the reason why the comparator is sensitive to PSN. So, the technique which is for balancing two input impedance is important to reduce PSN effects. We consider chip-PCB components to estimate two input impedance, because the two input impedances are affected by chip-PCB hierarchical structure. If we control the impedance of each input, we can design the ADC which is nonsensitive to PSN at the targeted frequency. We demonstrate the proposed technique based on simulation by PSN whose frequency swept from 1MHz to 3GHz.
{"title":"On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure","authors":"Bumhee Bae, Jonghyun Cho, Joungho Kim","doi":"10.1109/ISEMC.2012.6351672","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351672","url":null,"abstract":"In this paper, we propose the on-chip design techniques for controlling Power Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps for explaining the proposed design technique. First, we explain what the PSN coupling path is on ADC. The PSN will couple from noise source to noise victim via power distribution network and circuit path. Second, we propose how we can reduce the noise coupling effects. The comparator is essential circuit to ADC and most sensitive circuit to PSN in ADC. Therefore, it is important to reduce the noise coupling effects on comparator for designing ADC which is non-sensitive to PSN. The comparator has two input nodes, and the differential voltage between two input nodes affect to ADC output. The impedance imbalance between two comparator inputs is the reason why the comparator is sensitive to PSN. So, the technique which is for balancing two input impedance is important to reduce PSN effects. We consider chip-PCB components to estimate two input impedance, because the two input impedances are affected by chip-PCB hierarchical structure. If we control the impedance of each input, we can design the ADC which is nonsensitive to PSN at the targeted frequency. We demonstrate the proposed technique based on simulation by PSN whose frequency swept from 1MHz to 3GHz.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351829
E. Savage, W. Radasky
In this paper we present an overview of the IEMI threat, discuss an assessment approach, and present mitigation options. Because it is often dominant, we concentrate on cable coupling of radiated RF (radio frequency) power as the means of IEMI attack. We separate an IEMI attack into various parts, and introduce an efficient approach for assessing the IEMI vulnerability of a facility. We then present some methods to mitigate IEMI attacks, especially for network cable coupling. Finally, we review ongoing worldwide IEMI efforts.
{"title":"Overview of the threat of IEMI (intentional electromagnetic interference)","authors":"E. Savage, W. Radasky","doi":"10.1109/ISEMC.2012.6351829","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351829","url":null,"abstract":"In this paper we present an overview of the IEMI threat, discuss an assessment approach, and present mitigation options. Because it is often dominant, we concentrate on cable coupling of radiated RF (radio frequency) power as the means of IEMI attack. We separate an IEMI attack into various parts, and introduce an efficient approach for assessing the IEMI vulnerability of a facility. We then present some methods to mitigate IEMI attacks, especially for network cable coupling. Finally, we review ongoing worldwide IEMI efforts.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114121913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351665
J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki
This paper presents the feasibility of fault analysis using intentional electromagnetic interference (IEMI). Fault analysis (FA) is a kind of implementation attack that intentionally extracts a secret key embedded in a secure device such as a smart card. An attacker injects a computational fault during the cryptographic calculation and he can extract a secret key. Recently, Hayashi et al. showed that temporal faults could be remotely injected during the cryptographic calculation using IEMI. They showed a case study in which an Advanced Standard Encryption (AES) secret key could be extracted through fault analysis. However, the characteristics of faults that can be induced by IEMI were not described. And, a threat of various FAs was not clear. In this paper, we examine in detail how the IEMI fault injection affects the fault occurrence of intermediate states in a cryptographic module and investigate the distribution of the IEMI generated faults. Furthermore, we classify previous FAs with respect to an attack model such as the type of faults needed to achieve a successful attack, and discuss the feasibility of FAs using IEMI based on the experimental results.
{"title":"Feasibility of fault analysis based on intentional electromagnetic interference","authors":"J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki","doi":"10.1109/ISEMC.2012.6351665","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351665","url":null,"abstract":"This paper presents the feasibility of fault analysis using intentional electromagnetic interference (IEMI). Fault analysis (FA) is a kind of implementation attack that intentionally extracts a secret key embedded in a secure device such as a smart card. An attacker injects a computational fault during the cryptographic calculation and he can extract a secret key. Recently, Hayashi et al. showed that temporal faults could be remotely injected during the cryptographic calculation using IEMI. They showed a case study in which an Advanced Standard Encryption (AES) secret key could be extracted through fault analysis. However, the characteristics of faults that can be induced by IEMI were not described. And, a threat of various FAs was not clear. In this paper, we examine in detail how the IEMI fault injection affects the fault occurrence of intermediate states in a cryptographic module and investigate the distribution of the IEMI generated faults. Furthermore, we classify previous FAs with respect to an attack model such as the type of faults needed to achieve a successful attack, and discuss the feasibility of FAs using IEMI based on the experimental results.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351797
C. B. White
EMC test programs are often very lengthy and expensive. It is very important to address a number of critical EMC test issues as early in the program as possible to ensure complete and accurate planning, budgeting and design criteria. This paper presents and discusses a number of typical critical EMC test issues needing early resolution in programs. Suggestions are also provided to help control the potential impact of these issues.
{"title":"Critical EMC test issues needing early resolution","authors":"C. B. White","doi":"10.1109/ISEMC.2012.6351797","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351797","url":null,"abstract":"EMC test programs are often very lengthy and expensive. It is very important to address a number of critical EMC test issues as early in the program as possible to ensure complete and accurate planning, budgeting and design criteria. This paper presents and discusses a number of typical critical EMC test issues needing early resolution in programs. Suggestions are also provided to help control the potential impact of these issues.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123597468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351784
J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks
This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >;10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.
{"title":"ASIC package design optimization for 10 Gbps and above backplane serdes links","authors":"J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks","doi":"10.1109/ISEMC.2012.6351784","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351784","url":null,"abstract":"This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >;10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125243186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351807
N. Bondarenko, Peng Shao, A. Orlando, M. Koledintseva, D. Beetner, P. Berger
Bulk ferrite chokes are widely used to reduce common-mode (CM) currents on system harnesses. The impact of the ferrite on the CM currents depends on a variety of factors and is difficult to predict. A simple closed-form analytical model of the CM impedance of the ferrite that allows efficient evaluation of the impact of the ferrite is considered. In order to apply this model to a real active power system with cable harnesses, information about the system's CM loop impedance is measured using the minimally-invasive dual current clamp method. The predicted impact of the ferrite on the CM loop impedance of the system and the CM currents on the harness showed reasonable agreement with measurements in both a simple passive test setup and in a real active system.
{"title":"Prediction of common-mode current reduction using ferrites in systems with cable harnesses","authors":"N. Bondarenko, Peng Shao, A. Orlando, M. Koledintseva, D. Beetner, P. Berger","doi":"10.1109/ISEMC.2012.6351807","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351807","url":null,"abstract":"Bulk ferrite chokes are widely used to reduce common-mode (CM) currents on system harnesses. The impact of the ferrite on the CM currents depends on a variety of factors and is difficult to predict. A simple closed-form analytical model of the CM impedance of the ferrite that allows efficient evaluation of the impact of the ferrite is considered. In order to apply this model to a real active power system with cable harnesses, information about the system's CM loop impedance is measured using the minimally-invasive dual current clamp method. The predicted impact of the ferrite on the CM loop impedance of the system and the CM currents on the harness showed reasonable agreement with measurements in both a simple passive test setup and in a real active system.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351759
Ege Engin, Srinidhi Raghavan
This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxide-semiconductor (MOS) varactor capacitance. The results are validated against 2D quasi-static simulations and 3D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3D integrated system.
{"title":"Modeling of coupled TSVs in 3D ICs","authors":"Ege Engin, Srinidhi Raghavan","doi":"10.1109/ISEMC.2012.6351759","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351759","url":null,"abstract":"This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxide-semiconductor (MOS) varactor capacitance. The results are validated against 2D quasi-static simulations and 3D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3D integrated system.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351813
B. Rautio, Qiang Long, A. Agrawal, M. E. El Sabbagh
In this work, we present a novel methodology for geometric rasterization of arbitrary 3D planar geometries, and apply it to perform electromagnetic simulation based calibration for accurate high-frequency measurements of Graphene conductivity. The conductivity measurements may find application in the area of high-frequency Graphene-based circuits, specifically that of interconnects. Preliminary experimental and simulation results are shown and discussed.
{"title":"Simulation geometry rasterization for applications toward graphene interconnect characterization","authors":"B. Rautio, Qiang Long, A. Agrawal, M. E. El Sabbagh","doi":"10.1109/ISEMC.2012.6351813","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351813","url":null,"abstract":"In this work, we present a novel methodology for geometric rasterization of arbitrary 3D planar geometries, and apply it to perform electromagnetic simulation based calibration for accurate high-frequency measurements of Graphene conductivity. The conductivity measurements may find application in the area of high-frequency Graphene-based circuits, specifically that of interconnects. Preliminary experimental and simulation results are shown and discussed.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122316316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6351677
Jian-Yao Zhao, W. Yin, Ming-da Zhu, W. Luo
One adaptive method, based on time-domain E-PMCHW (Poggio, Miller, Chang, Harrington and Wu) integral equation, is presented for predicting transient scattering and radiation responses of some composite structures made of perfectly conducting (PEC) and dielectric materials. Both PEC and dielectric parts are described by the electric field integral equations (EFIE) and the PMCHW ones, respectively, with a set of time domain E-PMCHW equations derived. The common RWG and line basis functions are used to expand surface and wire currents, respectively. The derived equations are then solved by marching-on-in-order (MOO) procedure, where an alternative overall stopping criterion is used in an adaptive way. Some typical numerical results are given to demonstrate its accuracy in capturing transient scattering and radiation responses of some typical composites in the presence of an intentional electromagnetic pulse (IEMP).
提出了一种基于时域E-PMCHW (Poggio, Miller, Chang, Harrington and Wu)积分方程的自适应方法，用于预测某些完美导电材料与介电材料构成的复合结构的瞬态散射和辐射响应。分别用电场积分方程(EFIE)和PMCHW方程来描述电场和介电部分，并推导出一组时域E-PMCHW方程。常用的RWG和线基函数分别用于扩展表面电流和导线电流。然后，采用自适应方式采用备选总体停止准则的顺序行进(MOO)方法求解导出的方程。给出了一些典型的数值结果，证明了该方法能够准确地捕捉一些典型复合材料在意图电磁脉冲(IEMP)作用下的瞬态散射和辐射响应。
{"title":"Time domain E-PMCHW integral equation solved by adaptive marching-on-in-order procedure for predicting transient responses of some composite structures","authors":"Jian-Yao Zhao, W. Yin, Ming-da Zhu, W. Luo","doi":"10.1109/ISEMC.2012.6351677","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351677","url":null,"abstract":"One adaptive method, based on time-domain E-PMCHW (Poggio, Miller, Chang, Harrington and Wu) integral equation, is presented for predicting transient scattering and radiation responses of some composite structures made of perfectly conducting (PEC) and dielectric materials. Both PEC and dielectric parts are described by the electric field integral equations (EFIE) and the PMCHW ones, respectively, with a set of time domain E-PMCHW equations derived. The common RWG and line basis functions are used to expand surface and wire currents, respectively. The derived equations are then solved by marching-on-in-order (MOO) procedure, where an alternative overall stopping criterion is used in an adaptive way. Some typical numerical results are given to demonstrate its accuracy in capturing transient scattering and radiation responses of some typical composites in the presence of an intentional electromagnetic pulse (IEMP).","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/ISEMC.2012.6350920
F. Grassi, G. Spadacini, S. Pignari
This work deals with human exposure of workers to electromagnetic fields generated by manual arc-welding processes, and focuses on the comparison between current ICNIRP basic restrictions (2010), defined as internal electric field values, and previous ICNIRP basic restrictions (1998), still in force in the EU till the Directive 2004/40/EC will be revised, defined in terms of induced current density. To this aim, numerical simulation is used to mimic the exposure setup defined in Standard EN 50444, in the severe case of Tungsten Inert Gas (TIG) welding involving square-wave currents. It is shown that application of the new ICNIRP Guidelines leads to a significant reduction of the exposure index.
{"title":"Human exposure in arc-welding processes: Current versus previous ICNIRP basic restrictions","authors":"F. Grassi, G. Spadacini, S. Pignari","doi":"10.1109/ISEMC.2012.6350920","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6350920","url":null,"abstract":"This work deals with human exposure of workers to electromagnetic fields generated by manual arc-welding processes, and focuses on the comparison between current ICNIRP basic restrictions (2010), defined as internal electric field values, and previous ICNIRP basic restrictions (1998), still in force in the EU till the Directive 2004/40/EC will be revised, defined in terms of induced current density. To this aim, numerical simulation is used to mimic the exposure setup defined in Standard EN 50444, in the severe case of Tungsten Inert Gas (TIG) welding involving square-wave currents. It is shown that application of the new ICNIRP Guidelines leads to a significant reduction of the exposure index.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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