Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181678
Shiyi Xu, Jia-bi Chen
Random testing has been used for years in both software and hardware testing. It is well known that in random testing each test requires to be selected randomly regardless of the tests previously generated. However, random testing could be inefficient for its random selection of test patterns. This paper, based on random testing, introduces the concept of Maximum Distance Testing (MDT) for VLSI circuits in which the total distance among all test patterns is chosen maximal so that the set of faults detected by one test pattern is as different as possible from that of faults detected by the tests previously applied. The procedure for constructing a Maximum Distance Testing Sequence (MDTS) is described in detail. Experimental results on Benchmark as well as other circuits are also given to evaluate the performances of our new approach.
{"title":"Maximum distance testing","authors":"Shiyi Xu, Jia-bi Chen","doi":"10.1109/ATS.2002.1181678","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181678","url":null,"abstract":"Random testing has been used for years in both software and hardware testing. It is well known that in random testing each test requires to be selected randomly regardless of the tests previously generated. However, random testing could be inefficient for its random selection of test patterns. This paper, based on random testing, introduces the concept of Maximum Distance Testing (MDT) for VLSI circuits in which the total distance among all test patterns is chosen maximal so that the set of faults detected by one test pattern is as different as possible from that of faults detected by the tests previously applied. The procedure for constructing a Maximum Distance Testing Sequence (MDTS) is described in detail. Experimental results on Benchmark as well as other circuits are also given to evaluate the performances of our new approach.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181728
H. Date, Toshinori Hosokawa, M. Muraoka
This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.
{"title":"A SoC test strategy based on a non-scan DFT method","authors":"H. Date, Toshinori Hosokawa, M. Muraoka","doi":"10.1109/ATS.2002.1181728","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181728","url":null,"abstract":"This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125251742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181731
V. Iyengar, K. Chakrabarty, E. Marinissen
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.
{"title":"Recent advances in test planning for modular testing of core-based SOCs","authors":"V. Iyengar, K. Chakrabarty, E. Marinissen","doi":"10.1109/ATS.2002.1181731","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181731","url":null,"abstract":"Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131925492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181749
S. Upadhyaya, Jae Min Lee, Padmanabhan Nair
Testing and diagnosis of analog circuits continues to be a hard task for test engineers and efficient test methodologies to tackle these problems are needed. This paper proposes a novel analog test method using time slot specification (TSS) based built-in current sensors. A technique for location of a fault site and fault type, based on TSS, is presented. The proposed built-in current sense and decision module (BSDM), in association with TSS analysis, has high testability and good fault coverage, and a capability to diagnose catastrophic faults and parametric faults in analog circuits. The digital output of the BSDM can be easily combined with built-in digital test modules for mixed-signal IC testing. The general heuristics for test point placement are also described.
{"title":"Time slot specification based approach to analog fault diagnosis using built-in current sensors and test point insertion","authors":"S. Upadhyaya, Jae Min Lee, Padmanabhan Nair","doi":"10.1109/ATS.2002.1181749","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181749","url":null,"abstract":"Testing and diagnosis of analog circuits continues to be a hard task for test engineers and efficient test methodologies to tackle these problems are needed. This paper proposes a novel analog test method using time slot specification (TSS) based built-in current sensors. A technique for location of a fault site and fault type, based on TSS, is presented. The proposed built-in current sense and decision module (BSDM), in association with TSS analysis, has high testability and good fault coverage, and a capability to diagnose catastrophic faults and parametric faults in analog circuits. The digital output of the BSDM can be easily combined with built-in digital test modules for mixed-signal IC testing. The general heuristics for test point placement are also described.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"94 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181745
Yu Huang, S. Reddy, Wu Cheng
In this paper, a method is presented to schedule tests for core-based SoCs to achieve optimal test completion time for the SoC design by simultaneously determining optimal core clustering, core cluster wrapper width, and pin mapping. For the first time the above mentioned techniques are applied concurrently to solve the SoC test scheduling problem. A heuristic algorithm implementing these techniques to determine an optimal solution is proposed.
{"title":"Core-clustering based SoC test scheduling optimization","authors":"Yu Huang, S. Reddy, Wu Cheng","doi":"10.1109/ATS.2002.1181745","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181745","url":null,"abstract":"In this paper, a method is presented to schedule tests for core-based SoCs to achieve optimal test completion time for the SoC design by simultaneously determining optimal core clustering, core cluster wrapper width, and pin mapping. For the first time the above mentioned techniques are applied concurrently to solve the SoC test scheduling problem. A heuristic algorithm implementing these techniques to determine an optimal solution is proposed.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115959393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181732
Y. Higami, Shin-ya Kobayashi, Y. Takamatsu
For recent VLSIs designed for low power, reduction of power dissipation during test is one of the most important problems. This paper presents a method to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method, test vectors generated by ATPG are given and they are improved to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluated for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simulation and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS '89 benchmark circuits.
{"title":"A method to reduce power dissipation during test for sequential circuits","authors":"Y. Higami, Shin-ya Kobayashi, Y. Takamatsu","doi":"10.1109/ATS.2002.1181732","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181732","url":null,"abstract":"For recent VLSIs designed for low power, reduction of power dissipation during test is one of the most important problems. This paper presents a method to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method, test vectors generated by ATPG are given and they are improved to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluated for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simulation and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS '89 benchmark circuits.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116104763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181687
S. Kajihara, K. Taniguchi, K. Miyase, I. Pomeranz, S. Reddy
This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.
{"title":"Test data compression using don't-care identification and statistical encoding [logic testing]","authors":"S. Kajihara, K. Taniguchi, K. Miyase, I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2002.1181687","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181687","url":null,"abstract":"This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124728653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181743
Kazuhiro Yamada, Yoshikazu Takahashi
This paper describes a low-cost memory expansion system for the Advantest T33XX logic tester series. Using this system, the T33XX tester has the same capability as the T6672 tester. This system allows the T33XX to be used for ASIC wafer testing until 2010.
{"title":"Vector memory expansion system for T33XX logic tester","authors":"Kazuhiro Yamada, Yoshikazu Takahashi","doi":"10.1109/ATS.2002.1181743","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181743","url":null,"abstract":"This paper describes a low-cost memory expansion system for the Advantest T33XX logic tester series. Using this system, the T33XX tester has the same capability as the T6672 tester. This system allows the T33XX to be used for ASIC wafer testing until 2010.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130405538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181707
K. Shimizu, N. Itazaki, K. Kinoshita
In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic, that realizes any logic gate, has been proposed. Moreover, the domino logic has another drawback in that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of target fault reduction, considering conflicts of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic values without handling details of the timing events of circuits.
{"title":"Crosstalk fault reduction and simulation for clock-delayed domino circuits","authors":"K. Shimizu, N. Itazaki, K. Kinoshita","doi":"10.1109/ATS.2002.1181707","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181707","url":null,"abstract":"In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic, that realizes any logic gate, has been proposed. Moreover, the domino logic has another drawback in that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of target fault reduction, considering conflicts of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic values without handling details of the timing events of circuits.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131979980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181697
Lihong Tong, Kazuki Suzuki, Hideo Ito
In delay fault detection BIST (built-in-self-test), an adjacency test pattern generation scheme can generate robust test patterns effectively. Traditional adjacency test pattern generation schemes use an LFSR (linear feedback shift register) to generate initial vectors but they cannot handle circuits with more than 30 inputs. In this paper, a determined BIST scheme, where several seeds are applied, is proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used to generate the seeds - the small number of necessary initial vectors. Through combining outputs of the shift register, the number of shift register stages is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short lest time. The hardware overhead is at the same level as traditional methods.
{"title":"Optimal seed generation for delay fault detection BIST","authors":"Lihong Tong, Kazuki Suzuki, Hideo Ito","doi":"10.1109/ATS.2002.1181697","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181697","url":null,"abstract":"In delay fault detection BIST (built-in-self-test), an adjacency test pattern generation scheme can generate robust test patterns effectively. Traditional adjacency test pattern generation schemes use an LFSR (linear feedback shift register) to generate initial vectors but they cannot handle circuits with more than 30 inputs. In this paper, a determined BIST scheme, where several seeds are applied, is proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used to generate the seeds - the small number of necessary initial vectors. Through combining outputs of the shift register, the number of shift register stages is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short lest time. The hardware overhead is at the same level as traditional methods.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133076564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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