Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181704
S. Bhunia, Hai Helen Li, K. Roy
Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for a high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of gated-ground (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to the stacking effect of the transistor without significantly affecting performance. Simulation results for a 64 K cache show 20% average improvement in IDDQ sensitivity for TSMC 0.25 /spl mu/m technology, while the improvement is more than 1000% for the 70 nm predictive technology model.
{"title":"A high performance IDDQ testable cache for scaled CMOS technologies","authors":"S. Bhunia, Hai Helen Li, K. Roy","doi":"10.1109/ATS.2002.1181704","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181704","url":null,"abstract":"Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for a high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of gated-ground (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to the stacking effect of the transistor without significantly affecting performance. Simulation results for a 64 K cache show 20% average improvement in IDDQ sensitivity for TSMC 0.25 /spl mu/m technology, while the improvement is more than 1000% for the 70 nm predictive technology model.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134438229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181739
Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero
Design verification is a crucial step in the design of any electronic device. Particularly when microprocessor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test program for maximizing a given verification metric. The methodology is based on an evolutionary paradigm and exploits a syntactical description of microprocessor assembly language and an RT-level functional model. Experimental results show the effectiveness of the approach.
{"title":"Evolutionary test program induction for microprocessor design verification","authors":"Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero","doi":"10.1109/ATS.2002.1181739","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181739","url":null,"abstract":"Design verification is a crucial step in the design of any electronic device. Particularly when microprocessor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test program for maximizing a given verification metric. The methodology is based on an evolutionary paradigm and exploits a syntactical description of microprocessor assembly language and an RT-level functional model. Experimental results show the effectiveness of the approach.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132057828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181738
T. Jiang, C. Liu, Jing-Yang Jou
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in. The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.
{"title":"Effective error diagnosis for RTL designs in HDLs","authors":"T. Jiang, C. Liu, Jing-Yang Jou","doi":"10.1109/ATS.2002.1181738","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181738","url":null,"abstract":"We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in. The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127854371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181694
Z. Al-Ars, A. V. Goor
To limit the exponential complexity required to analyze the dynamic faulty behavior of DRAMs, algorithms have been published to approximate the faulty behavior of DRAM cell defects. These algorithms, however, have limited practical application since they are based on generic memory operations (writes and reads) rather than the DRAM specific operations (activation, precharge, etc.). This paper extends the approximation algorithms by incorporating the DRAM specific operations, making them directly applicable in practice. In addition, based on the new extended method, the paper shows results of a fault analysis study of cell defects using electrical simulation.
{"title":"DRAM specific approximation of the faulty behavior of cell defects","authors":"Z. Al-Ars, A. V. Goor","doi":"10.1109/ATS.2002.1181694","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181694","url":null,"abstract":"To limit the exponential complexity required to analyze the dynamic faulty behavior of DRAMs, algorithms have been published to approximate the faulty behavior of DRAM cell defects. These algorithms, however, have limited practical application since they are based on generic memory operations (writes and reads) rather than the DRAM specific operations (activation, precharge, etc.). This paper extends the approximation algorithms by incorporating the DRAM specific operations, making them directly applicable in practice. In addition, based on the new extended method, the paper shows results of a fault analysis study of cell defects using electrical simulation.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128445373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181711
Nan Li, Sying-Jyan Wang
In this paper, we describe a new design methodology for LFSR-based test pattern generators (TPG). Multiple seeds are produced by the TPG itself to deal with hard-to-detect faults, and this function is achieved without using a ROM to store the seeds. A reseeding logic is incorporated in the TPG, which loads new seeds into the LFSR whenever specific states are reached. In this way, useless test vectors are skipped and thus the test application time can be greatly reduced. We experiment the design methodology by applying it to some MCNC benchmark circuits, and the results show that TPGs designed with this technique require much less hardware overhead than the previous known reseeding techniques.
{"title":"A reseeding technique for LFSR-based BIST applications","authors":"Nan Li, Sying-Jyan Wang","doi":"10.1109/ATS.2002.1181711","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181711","url":null,"abstract":"In this paper, we describe a new design methodology for LFSR-based test pattern generators (TPG). Multiple seeds are produced by the TPG itself to deal with hard-to-detect faults, and this function is achieved without using a ROM to store the seeds. A reseeding logic is incorporated in the TPG, which loads new seeds into the LFSR whenever specific states are reached. In this way, useless test vectors are skipped and thus the test application time can be greatly reduced. We experiment the design methodology by applying it to some MCNC benchmark circuits, and the results show that TPGs designed with this technique require much less hardware overhead than the previous known reseeding techniques.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181703
Zhao Xuemei, Ye Yi-zheng, C. Chunxu
A new efficient test approach of functional faults in word-oriented content addressable memories (CAM) is presented. New functional fault models of CAM, based on physical defects are given, taken from traditional functional fault models for SRAM. All functional faults of CAM are classified into OR faults (ORFs) and AND faults (ANDFs). To test intra-word and inter-word faults, different data background sequences for word-oriented CAM are proposed. A whole test strategy, include three steps, is presented to test word-oriented dual-port CAMs thoroughly.
{"title":"Tests for word-oriented content addressable memories","authors":"Zhao Xuemei, Ye Yi-zheng, C. Chunxu","doi":"10.1109/ATS.2002.1181703","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181703","url":null,"abstract":"A new efficient test approach of functional faults in word-oriented content addressable memories (CAM) is presented. New functional fault models of CAM, based on physical defects are given, taken from traditional functional fault models for SRAM. All functional faults of CAM are classified into OR faults (ORFs) and AND faults (ANDFs). To test intra-word and inter-word faults, different data background sequences for word-oriented CAM are proposed. A whole test strategy, include three steps, is presented to test word-oriented dual-port CAMs thoroughly.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181744
E. Larsson, Klas Arvidsson, H. Fujiwara, Zebo Peng
We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design to minimize the test time and the TAM routing cost while considering test conflicts and power constraints. The main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.
{"title":"Integrated test scheduling, test parallelization and TAM design","authors":"E. Larsson, Klas Arvidsson, H. Fujiwara, Zebo Peng","doi":"10.1109/ATS.2002.1181744","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181744","url":null,"abstract":"We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design to minimize the test time and the TAM routing cost while considering test conflicts and power constraints. The main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132178097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181746
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Y. Lin
We propose an efficient test scheduling and test access architecture for system-on-chip. The test time and test control complexity are optimized under the test power and test access mechanism (TAM) resource constraints. Using our heuristic algorithms, the test scheduling can be done rapidly with small test time penalty when compared with previous works. Under an existing SoC test framework, the test access hardware can be generated from the scheduling result. Experimental results show that the proposed scheduling is hardware efficient. The system integrator can evaluate the test access architecture and perform rest scheduling systematically.
{"title":"Test scheduling and test access architecture optimization for system-on-chip","authors":"Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Y. Lin","doi":"10.1109/ATS.2002.1181746","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181746","url":null,"abstract":"We propose an efficient test scheduling and test access architecture for system-on-chip. The test time and test control complexity are optimized under the test power and test access mechanism (TAM) resource constraints. Using our heuristic algorithms, the test scheduling can be done rapidly with small test time penalty when compared with previous works. Under an existing SoC test framework, the test access hardware can be generated from the scheduling result. Experimental results show that the proposed scheduling is hardware efficient. The system integrator can evaluate the test access architecture and perform rest scheduling systematically.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132182455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181719
Shi-Yu Huang
This paper addresses the problem of locating the stuck-open faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty signals, our goal is to further narrow down the faults to a few suspected segments. With such a technique, the silicon inspection time could be dramatically slashed when the fault occurs to a long-running wire with a large number of fanouts. The algorithm is based on our previous inject-and-evaluate paradigm using symbolic simulation. It is fast and accurate. For ISCAS85 benchmark circuits with only one stuck-open fault, the first-hit index is 4.5 on the average within 10 seconds of CPU time.
{"title":"Diagnosis of Byzantine open-segment faults [scan testing]","authors":"Shi-Yu Huang","doi":"10.1109/ATS.2002.1181719","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181719","url":null,"abstract":"This paper addresses the problem of locating the stuck-open faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty signals, our goal is to further narrow down the faults to a few suspected segments. With such a technique, the silicon inspection time could be dramatically slashed when the fault occurs to a long-running wire with a large number of fanouts. The algorithm is based on our previous inject-and-evaluate paradigm using symbolic simulation. It is fast and accurate. For ISCAS85 benchmark circuits with only one stuck-open fault, the first-hit index is 4.5 on the average within 10 seconds of CPU time.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124954000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181705
Wichian Sirisaengtaksin, S. Gupta
In this paper we develop a new fault model for capacitive crosstalk in inter-core interconnects. We also develop a framework to generate compact tests for interconnects with arbitrary topologies. Experimental results show that the proposed approach can significantly reduce test application time for large interconnects. We are in the process of extending the framework to interconnects that include tri-state as well as bi-directional nets.
{"title":"Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology","authors":"Wichian Sirisaengtaksin, S. Gupta","doi":"10.1109/ATS.2002.1181705","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181705","url":null,"abstract":"In this paper we develop a new fault model for capacitive crosstalk in inter-core interconnects. We also develop a framework to generate compact tests for interconnects with arbitrary topologies. Experimental results show that the proposed approach can significantly reduce test application time for large interconnects. We are in the process of extending the framework to interconnects that include tri-state as well as bi-directional nets.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129465668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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