Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181683
M. Ishida, Takahiro J. Yamaguchi, M. Soma, H. Musha
This paper presents an experimental study of random jitter modulation in a commercial serializer-deserializer device to demonstrate the effects of possible amplitude modulation in jitter tolerance measurements. The paper recommends alternative methods for injecting random jitter to avoid this source of measurement error.
{"title":"Effects of amplitude modulation in jitter tolerance measurements of communication devices","authors":"M. Ishida, Takahiro J. Yamaguchi, M. Soma, H. Musha","doi":"10.1109/ATS.2002.1181683","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181683","url":null,"abstract":"This paper presents an experimental study of random jitter modulation in a commercial serializer-deserializer device to demonstrate the effects of possible amplitude modulation in jitter tolerance measurements. The paper recommends alternative methods for injecting random jitter to avoid this source of measurement error.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181721
Niloy Ganguly, Anindya Nandi, Sukanta Das, B. Sikdar, P. P. Chaudhuri
This paper reports the design of an on-chip Test Pattern Generator (TPG) for VLSI circuits that avoids generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. The theoretical framework of CA has provided the foundation of this work. A GA based evolution scheme is employed to achieve the desired TPG developed over the theory of cellular automata.
{"title":"An evolutionary strategy to design an on-chip test pattern generator without prohibited pattern set (PPS)","authors":"Niloy Ganguly, Anindya Nandi, Sukanta Das, B. Sikdar, P. P. Chaudhuri","doi":"10.1109/ATS.2002.1181721","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181721","url":null,"abstract":"This paper reports the design of an on-chip Test Pattern Generator (TPG) for VLSI circuits that avoids generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. The theoretical framework of CA has provided the foundation of this work. A GA based evolution scheme is employed to achieve the desired TPG developed over the theory of cellular automata.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181713
Min-Kyu Joo, Jin-Hyung Kim, Yoon-Hwa Choi
Secure transmission over wireline/wireless networks requires encryption of data and control information. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service and side-channel attacks. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmetric block ciphers. It detects errors, locates the corresponding faults, and readily reconfigures during normal operation, to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlled by properly choosing the number of extra stages. Moreover, fault tolerance is achieved with negligible time overhead.
{"title":"A fault-tolerant architecture for symmetric block ciphers","authors":"Min-Kyu Joo, Jin-Hyung Kim, Yoon-Hwa Choi","doi":"10.1109/ATS.2002.1181713","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181713","url":null,"abstract":"Secure transmission over wireline/wireless networks requires encryption of data and control information. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service and side-channel attacks. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmetric block ciphers. It detects errors, locates the corresponding faults, and readily reconfigures during normal operation, to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlled by properly choosing the number of extra stages. Moreover, fault tolerance is achieved with negligible time overhead.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114871894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181701
P. Zhongliang
A new testable design method for arbitrary logic functions is presented. The method employs AND gate arrays and XOR gate trees to realize the ESOP (EXOR-sum-of-products) expressions of logic functions. This significantly reduces the delay as compared with using cascaded XOR gates. It is shown that only n+5 test vectors are required to detect any single fault in the circuit realizations, and these tests are independent of the logic functions being realized, where n is the number of input variables. Multiple fault defects in the circuit realizations are studied, and a multiple faults test set is given. The test set can be generated easily. The method proposed in this paper is more versatile than those based on other function expression forms, since the ESOP is the most general form and it can give a small number of product terms.
{"title":"Testable realizations for ESOP expressions of logic functions","authors":"P. Zhongliang","doi":"10.1109/ATS.2002.1181701","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181701","url":null,"abstract":"A new testable design method for arbitrary logic functions is presented. The method employs AND gate arrays and XOR gate trees to realize the ESOP (EXOR-sum-of-products) expressions of logic functions. This significantly reduces the delay as compared with using cascaded XOR gates. It is shown that only n+5 test vectors are required to detect any single fault in the circuit realizations, and these tests are independent of the logic functions being realized, where n is the number of input variables. Multiple fault defects in the circuit realizations are studied, and a multiple faults test set is given. The test set can be generated easily. The method proposed in this paper is more versatile than those based on other function expression forms, since the ESOP is the most general form and it can give a small number of product terms.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122078635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181715
F. Vargas, R. Fagundes, D. Barros
In this paper, we present the last improvements for a new approach to cope with noise that troubles speech recognition systems (SRS). This approach performs on-line monitoring and is oriented to hardware redundancy (it is essentially a modification of the classic recovery block scheme). When compared to conventional approaches using fast Fourier transforms (FFT) and Hamming code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably lower complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running on a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. A last implementation was prototyped on a hardware/software development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera component.
{"title":"Experimental results of a recovery block scheme to handle noise in speech recognition systems","authors":"F. Vargas, R. Fagundes, D. Barros","doi":"10.1109/ATS.2002.1181715","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181715","url":null,"abstract":"In this paper, we present the last improvements for a new approach to cope with noise that troubles speech recognition systems (SRS). This approach performs on-line monitoring and is oriented to hardware redundancy (it is essentially a modification of the classic recovery block scheme). When compared to conventional approaches using fast Fourier transforms (FFT) and Hamming code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably lower complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running on a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. A last implementation was prototyped on a hardware/software development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera component.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"740 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181676
Yun Shao, I. Pomeranz, S. Reddy
In this work we propose a path-oriented test generation procedure called POTENT to generate high quality tests for transition faults. Both weak non-robust and strong non-robust tests can be generated by POTENT. We classify, transition fault tests into six types according to their activation and propagation methods. The basic idea of POTENT is to test a transition fault along a longest testable path passing through the fault site. For transition faults that are activated or propagated through multipaths, heuristics are proposed to maximize the propagation delay of the target fault. We also propose an efficient method to evaluate the quality of a given transition fault test set. Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.
{"title":"On generating high quality tests for transition faults","authors":"Yun Shao, I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2002.1181676","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181676","url":null,"abstract":"In this work we propose a path-oriented test generation procedure called POTENT to generate high quality tests for transition faults. Both weak non-robust and strong non-robust tests can be generated by POTENT. We classify, transition fault tests into six types according to their activation and propagation methods. The basic idea of POTENT is to test a transition fault along a longest testable path passing through the fault site. For transition faults that are activated or propagated through multipaths, heuristics are proposed to maximize the propagation delay of the target fault. We also propose an efficient method to evaluate the quality of a given transition fault test set. Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181709
S. Chattopadhyay
Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. Since it does not assume any fault model, the testing ensures detection of all static detectable faults in the circuit that do not require two-pattern tests. Earlier works on pseudoexhaustive testing usually generate test sets that are several orders of magnitude larger than the minimum size test set required for a specific circuit, and are mostly based on LFSRs. This paper presents a novel strategy for constructing circuit-specific pseudoexhaustive test pattern generators, based on cellular automata, that result in generating minimal pseudoexhaustive test sets for combinational circuits. Experimentation with ISCAS85 benchmarks show that as compared to the LFSRs, the cellular automata based approach often results in simpler circuitry with lesser number of shift stages and reduced test length. Moreover, the analytical technique developed here is generic in nature and thus can also be applied for constructing LFSR based pseudoexhaustive test pattern generators.
{"title":"Efficient circuit specific pseudoexhaustive testing with cellular automata","authors":"S. Chattopadhyay","doi":"10.1109/ATS.2002.1181709","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181709","url":null,"abstract":"Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. Since it does not assume any fault model, the testing ensures detection of all static detectable faults in the circuit that do not require two-pattern tests. Earlier works on pseudoexhaustive testing usually generate test sets that are several orders of magnitude larger than the minimum size test set required for a specific circuit, and are mostly based on LFSRs. This paper presents a novel strategy for constructing circuit-specific pseudoexhaustive test pattern generators, based on cellular automata, that result in generating minimal pseudoexhaustive test sets for combinational circuits. Experimentation with ISCAS85 benchmarks show that as compared to the LFSRs, the cellular automata based approach often results in simpler circuitry with lesser number of shift stages and reduced test length. Moreover, the analytical technique developed here is generic in nature and thus can also be applied for constructing LFSR based pseudoexhaustive test pattern generators.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"98 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181729
K. Iijima, A. Akar, C. McDonald, D. Burek
The cost of test for SoCs (system-on-chips) is tremendous, especially for large and complex designs. Although the high price of ATE (Automatic Test Equipment) is recognized as the primary contributor of test cost, and is therefore most highlighted, high test costs are also caused by factors related to engineering flows ranging from design to manufacturing. In this paper, the discussion will focus on test cost reduction, with all such factors taken into account. A potential difficulty in this discussion is that it is generally difficult to achieve higher quality and lower cost at the same time. In working with several leading edge semiconductor companies in the United States and Japan, the authors have observed and analyzed the whole picture of current flows in design and manufacturing test, including quantitative study of the cost of test. Based upon the results of this analysis, a proposed solution is analyzed, based upon effectiveness in achieving two goals: higher quality and lower costs.
{"title":"Embedded test solution as a breakthrough in reducing cost of test for system on chips","authors":"K. Iijima, A. Akar, C. McDonald, D. Burek","doi":"10.1109/ATS.2002.1181729","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181729","url":null,"abstract":"The cost of test for SoCs (system-on-chips) is tremendous, especially for large and complex designs. Although the high price of ATE (Automatic Test Equipment) is recognized as the primary contributor of test cost, and is therefore most highlighted, high test costs are also caused by factors related to engineering flows ranging from design to manufacturing. In this paper, the discussion will focus on test cost reduction, with all such factors taken into account. A potential difficulty in this discussion is that it is generally difficult to achieve higher quality and lower cost at the same time. In working with several leading edge semiconductor companies in the United States and Japan, the authors have observed and analyzed the whole picture of current flows in design and manufacturing test, including quantitative study of the cost of test. Based upon the results of this analysis, a proposed solution is analyzed, based upon effectiveness in achieving two goals: higher quality and lower costs.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131986188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181731
V. Iyengar, K. Chakrabarty, E. Marinissen
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.
{"title":"Recent advances in test planning for modular testing of core-based SOCs","authors":"V. Iyengar, K. Chakrabarty, E. Marinissen","doi":"10.1109/ATS.2002.1181731","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181731","url":null,"abstract":"Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131925492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181728
H. Date, Toshinori Hosokawa, M. Muraoka
This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.
{"title":"A SoC test strategy based on a non-scan DFT method","authors":"H. Date, Toshinori Hosokawa, M. Muraoka","doi":"10.1109/ATS.2002.1181728","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181728","url":null,"abstract":"This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125251742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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