Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181684
Hao-Chiao Hong, Jiun-Lang Huang, K. Cheng, Cheng-Wen Wu
Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.
{"title":"On-chip analog response extraction with 1-bit /spl Sigma/-/spl Delta/ modulators","authors":"Hao-Chiao Hong, Jiun-Lang Huang, K. Cheng, Cheng-Wen Wu","doi":"10.1109/ATS.2002.1181684","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181684","url":null,"abstract":"Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125464208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181718
K. Keller, Hiroshi Takahashi, K. T. Le, K. Saluja, Y. Takamatsu
We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults.
{"title":"Reduction of target fault list for crosstalk-induced delay faults by using layout constraints","authors":"K. Keller, Hiroshi Takahashi, K. T. Le, K. Saluja, Y. Takamatsu","doi":"10.1109/ATS.2002.1181718","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181718","url":null,"abstract":"We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181677
I. Polian, I. Pomeranz, B. Becker
n-detection test sets for stuck-at faults have been shown to be useful in detecting unmodeled defects. It was also shown that a set of faults, called maximally dominating faults, can play an important role in controlling the increase in the size of an n-detection test set as n is increased. In an earlier work, a superset of the maximally dominating fault set was used. In this work, we propose a method to determine exact sets of maximally dominating faults. We also define a new type of n-detection test sets based on the exact set of maximally dominating faults. We present experimental results to demonstrate the usefulness of this exact set in producing high-quality n-detection test sets.
{"title":"Exact computation of maximally dominating faults and its application to n-detection tests","authors":"I. Polian, I. Pomeranz, B. Becker","doi":"10.1109/ATS.2002.1181677","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181677","url":null,"abstract":"n-detection test sets for stuck-at faults have been shown to be useful in detecting unmodeled defects. It was also shown that a set of faults, called maximally dominating faults, can play an important role in controlling the increase in the size of an n-detection test set as n is increased. In an earlier work, a superset of the maximally dominating fault set was used. In this work, we propose a method to determine exact sets of maximally dominating faults. We also define a new type of n-detection test sets based on the exact set of maximally dominating faults. We present experimental results to demonstrate the usefulness of this exact set in producing high-quality n-detection test sets.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133971899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181727
Masayoshi Yoshimura, Toshinori Hosokawa, M. Ohta
The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.
{"title":"A test point insertion method to reduce the number of test patterns","authors":"Masayoshi Yoshimura, Toshinori Hosokawa, M. Ohta","doi":"10.1109/ATS.2002.1181727","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181727","url":null,"abstract":"The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131541917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181700
Y. Makris, A. Orailoglu
We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for reducing the cost of hierarchical test path construction. Test requirements are defined as a set of fine-grained input and output bit clusters and pertinent symbolic values. They are independent of actual test sets and are adjusted to the inherent module connectivity and regularity. As a result, they combine the generality required for fast hierarchical test path construction with the precision necessary for minimizing the incurred cost, thus fostering cost-effective hierarchical test.
{"title":"Test requirement analysis for low cost hierarchical test path construction","authors":"Y. Makris, A. Orailoglu","doi":"10.1109/ATS.2002.1181700","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181700","url":null,"abstract":"We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for reducing the cost of hierarchical test path construction. Test requirements are defined as a set of fine-grained input and output bit clusters and pertinent symbolic values. They are independent of actual test sets and are adjusted to the inherent module connectivity and regularity. As a result, they combine the generality required for fast hierarchical test path construction with the precision necessary for minimizing the incurred cost, thus fostering cost-effective hierarchical test.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181726
K. Hatayama, M. Nakao, Yasuo Sato
This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.
{"title":"At-speed built-in test for logic circuits with multiple clocks","authors":"K. Hatayama, M. Nakao, Yasuo Sato","doi":"10.1109/ATS.2002.1181726","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181726","url":null,"abstract":"This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181706
M. Wu, Chung-Len Lee, C. Chang, Jwu-E Chen
A test scheme for crosstalk faults, based on an oscillation signal, is proposed. It uses an oscillation signal applied to an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issues during test generation for crosstalk faults in conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.
{"title":"A testing scheme for crosstalk faults based on the oscillation test signal [VLSI]","authors":"M. Wu, Chung-Len Lee, C. Chang, Jwu-E Chen","doi":"10.1109/ATS.2002.1181706","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181706","url":null,"abstract":"A test scheme for crosstalk faults, based on an oscillation signal, is proposed. It uses an oscillation signal applied to an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issues during test generation for crosstalk faults in conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181712
E. Kalligeros, X. Kavousianos, D. Nikolos
In this paper, we present a new LFSR reseeding scheme for scan-based BIST, suitable for circuits with random-pattern-resistant faults. The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register. A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point. This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead. Experimental results on ISCAS '85 and ISCAS '89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time.
{"title":"A ROMless LFSR reseeding scheme for scan-based BIST","authors":"E. Kalligeros, X. Kavousianos, D. Nikolos","doi":"10.1109/ATS.2002.1181712","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181712","url":null,"abstract":"In this paper, we present a new LFSR reseeding scheme for scan-based BIST, suitable for circuits with random-pattern-resistant faults. The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register. A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point. This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead. Experimental results on ISCAS '85 and ISCAS '89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114540961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181681
P. Drineas, Y. Makris
We propose a methodology for the non-intrusive design of concurrently self-testable FSMs. The proposed method is similar to duplication, wherein a replica of the original FSM acts as a predictor that immediately detects potential faults by comparison to the original FSM. However, instead of duplicating the complete FSM, the proposed method replicates only a minimal portion adequate to detect all possible faults, yet at the cost of introducing potential fault detection latency. Furthermore, in contrast to concurrent error detection approaches, which presume the ability to re-synthesize the FSM and exploit parity-based state encoding, the proposed method is non-intrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results on FSMs of various sizes and densities indicate that the proposed method detects 100% of the faults with very low average fault detection latency. Furthermore, a hardware overhead reduction of up to 33% is achieved, as compared to duplication-based concurrent error detection.
{"title":"Non-intrusive design of concurrently self-testable FSMs","authors":"P. Drineas, Y. Makris","doi":"10.1109/ATS.2002.1181681","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181681","url":null,"abstract":"We propose a methodology for the non-intrusive design of concurrently self-testable FSMs. The proposed method is similar to duplication, wherein a replica of the original FSM acts as a predictor that immediately detects potential faults by comparison to the original FSM. However, instead of duplicating the complete FSM, the proposed method replicates only a minimal portion adequate to detect all possible faults, yet at the cost of introducing potential fault detection latency. Furthermore, in contrast to concurrent error detection approaches, which presume the ability to re-synthesize the FSM and exploit parity-based state encoding, the proposed method is non-intrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results on FSMs of various sizes and densities indicate that the proposed method detects 100% of the faults with very low average fault detection latency. Furthermore, a hardware overhead reduction of up to 33% is achieved, as compared to duplication-based concurrent error detection.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130549572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181698
O. Petre, H. Kerkhoff
During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.
{"title":"On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications","authors":"O. Petre, H. Kerkhoff","doi":"10.1109/ATS.2002.1181698","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181698","url":null,"abstract":"During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133949172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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