Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181690
T. Yoshida, M. Watari
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (multi duty-scan) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.
{"title":"MD-SCAN method for low power scan testing","authors":"T. Yoshida, M. Watari","doi":"10.1109/ATS.2002.1181690","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181690","url":null,"abstract":"As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (multi duty-scan) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181730
R. Kapur, T. Williams
In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.
{"title":"Manufacturing test of SoCs","authors":"R. Kapur, T. Williams","doi":"10.1109/ATS.2002.1181730","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181730","url":null,"abstract":"In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125615519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181680
Jing-ling Yang, O. Choy, C. Chan, K. Pun
This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.
{"title":"A totally self-checking dynamic asynchronous datapath","authors":"Jing-ling Yang, O. Choy, C. Chan, K. Pun","doi":"10.1109/ATS.2002.1181680","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181680","url":null,"abstract":"This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"413 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124419162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181708
M. Phadoongsidhi, K. T. Le, K. Saluja
Existing principles for crosstalk fault simulation require the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique, introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS'89 benchmark circuits show that a substantial improvement in CPU time, over a conventional method, is achieved with a trade-off in the amount of memory consumed.
{"title":"A concurrent fault simulation for crosstalk faults in sequential circuits","authors":"M. Phadoongsidhi, K. T. Le, K. Saluja","doi":"10.1109/ATS.2002.1181708","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181708","url":null,"abstract":"Existing principles for crosstalk fault simulation require the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique, introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS'89 benchmark circuits show that a substantial improvement in CPU time, over a conventional method, is achieved with a trade-off in the amount of memory consumed.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133943055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181702
Hong-Sik Kim, Sungho Kang
We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signatures. This paper describes how to convert a traditional March algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.
{"title":"DPSC SRAM transparent test algorithm","authors":"Hong-Sik Kim, Sungho Kang","doi":"10.1109/ATS.2002.1181702","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181702","url":null,"abstract":"We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signatures. This paper describes how to convert a traditional March algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129482568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181685
Toshinori Hosokawa, H. Date, M. Muraoka
This paper proposes a state reduction method for non-scan based FSM (finite state machine) testing with a don't care inputs identification technique. States for FSM testing are classified into valid test states and invalid test states. This method reduces the numbers of invalid test states and valid test states using a don't care input identification technique and a state compaction technique. The test length may be shortened by reducing the number of valid test states and additional test area is reduced by reducing the number of invalid test states. Experimental results for MCNC'91 FSM benchmarks and practical FSMs show that the proposed method reduces the test area by 13 to 77% and shortens the test lengths by 10 to 36%.
{"title":"A state reduction method for non-scan based FSM testing with don't care inputs identification technique","authors":"Toshinori Hosokawa, H. Date, M. Muraoka","doi":"10.1109/ATS.2002.1181685","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181685","url":null,"abstract":"This paper proposes a state reduction method for non-scan based FSM (finite state machine) testing with a don't care inputs identification technique. States for FSM testing are classified into valid test states and invalid test states. This method reduces the numbers of invalid test states and valid test states using a don't care input identification technique and a state compaction technique. The test length may be shortened by reducing the number of valid test states and additional test area is reduced by reducing the number of invalid test states. Experimental results for MCNC'91 FSM benchmarks and practical FSMs show that the proposed method reduces the test area by 13 to 77% and shortens the test lengths by 10 to 36%.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116025303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181733
Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Y. Min
Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.
{"title":"Test power optimization techniques for CMOS circuits","authors":"Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Y. Min","doi":"10.1109/ATS.2002.1181733","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181733","url":null,"abstract":"Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116067028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181748
H. Yotsuyanagi, M. Hashizume, T. Tamesada
In this paper, test time reduction for I/sub DDQ/ testing is discussed. Although I/sub DDQ/ testing is known to be effective in detecting faults in CMOS circuits, the test time of I/sub DDQ/ testing is larger than that of logic testing. It is shown that the test time of I/sub DDQ/ test mostly depends on the switching current. To reduce the test time of I/sub DDQ/ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.
{"title":"Test time reduction for I/sub DDQ/ testing by arranging test vectors","authors":"H. Yotsuyanagi, M. Hashizume, T. Tamesada","doi":"10.1109/ATS.2002.1181748","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181748","url":null,"abstract":"In this paper, test time reduction for I/sub DDQ/ testing is discussed. Although I/sub DDQ/ testing is known to be effective in detecting faults in CMOS circuits, the test time of I/sub DDQ/ testing is larger than that of logic testing. It is shown that the test time of I/sub DDQ/ test mostly depends on the switching current. To reduce the test time of I/sub DDQ/ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181723
S. Amasaki, Takashi Yoshitomi, O. Mizuno, T. Kikuno, Yasunari Takagi
According to a progress of the software process improvement, the time series data on the number of faults detected by the software testing are collected extensively. In this paper, we perform statistical analyses of relationships between the time series data and the field quality of software products. At first, we apply the rank correlation coefficient /spl tau/ to the time series data collected from actual software testing in a certain company, and classify these data into four types of trends: strict increasing, almost increasing, almost decreasing, and strict decreasing. We then investigate, for each type of trend, the field quality of software products developed by the corresponding software projects. As a result of statistical analyses, we showed that software projects having trend of almost or strict decreasing in the number of faults detected by the software testing could produce the software products with high quality.
{"title":"Statistical analysis of time series data on the number of faults detected by software testing","authors":"S. Amasaki, Takashi Yoshitomi, O. Mizuno, T. Kikuno, Yasunari Takagi","doi":"10.1109/ATS.2002.1181723","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181723","url":null,"abstract":"According to a progress of the software process improvement, the time series data on the number of faults detected by the software testing are collected extensively. In this paper, we perform statistical analyses of relationships between the time series data and the field quality of software products. At first, we apply the rank correlation coefficient /spl tau/ to the time series data collected from actual software testing in a certain company, and classify these data into four types of trends: strict increasing, almost increasing, almost decreasing, and strict decreasing. We then investigate, for each type of trend, the field quality of software products developed by the corresponding software projects. As a result of statistical analyses, we showed that software projects having trend of almost or strict decreasing in the number of faults detected by the software testing could produce the software products with high quality.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126422312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181695
Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang
As deep sub-micron techniques evolve, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to access limitations. To solve the testing problem, BIST circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. Based on the dual-slope principle, a new memory access time measurement unit for embedded memories with separate time-to-voltage and voltage-to-time architecture is proposed in this paper to achieve at-speed measurement with 50 ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262/spl times/92 /spl mu/m/sup 2/ under a 0.35 /spl mu/m 2P4M CMOS process.
{"title":"An access timing measurement unit of embedded memory","authors":"Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang","doi":"10.1109/ATS.2002.1181695","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181695","url":null,"abstract":"As deep sub-micron techniques evolve, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to access limitations. To solve the testing problem, BIST circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. Based on the dual-slope principle, a new memory access time measurement unit for embedded memories with separate time-to-voltage and voltage-to-time architecture is proposed in this paper to achieve at-speed measurement with 50 ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262/spl times/92 /spl mu/m/sup 2/ under a 0.35 /spl mu/m 2P4M CMOS process.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129478381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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