Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181724
Jin-Cherng Lin, Szu-Wen Lin
Software testability, which has been discussed in the past decade, has been defined as provisions that can be taken into consideration at the early step of software development. This paper gives software testability, previously defined by Voas, a new model and measurement without performing testing with respect to a particular input distribution.
{"title":"An analytic software testability model","authors":"Jin-Cherng Lin, Szu-Wen Lin","doi":"10.1109/ATS.2002.1181724","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181724","url":null,"abstract":"Software testability, which has been discussed in the past decade, has been defined as provisions that can be taken into consideration at the early step of software development. This paper gives software testability, previously defined by Voas, a new model and measurement without performing testing with respect to a particular input distribution.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132537633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181689
Atlaf Ul Amin, S. Ohtake, H. Fujiwara
This paper introduces a design for testability, (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. Firstly, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated into the circuit. Our approach is mostly based on a path delay fault model. However, the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases proportionally with increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.
{"title":"Design for two-pattern testability of controller-data path circuits","authors":"Atlaf Ul Amin, S. Ohtake, H. Fujiwara","doi":"10.1109/ATS.2002.1181689","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181689","url":null,"abstract":"This paper introduces a design for testability, (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. Firstly, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated into the circuit. Our approach is mostly based on a path delay fault model. However, the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases proportionally with increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130520545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181742
R. Rajsuman
For first silicon, detection of systematic defects, timing failure and other errors is an extremely time-pressured task because detection and debugging of such failures determines how fast a product can go into mass production. In this paper we describe a new method for this purpose using an event tester. This method allows testing in the same environment as used for the original simulation in which the chip was designed. The method uses original design simulation data directly from the Verilog/VHDL simulation in the VCD format and thus, eliminates test program generation and test vector translation processes into WGL/STIL or ATE formats. It essentially extends the EDA design environment to the physical testing of an IC.
{"title":"Extending EDA environment from design to test","authors":"R. Rajsuman","doi":"10.1109/ATS.2002.1181742","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181742","url":null,"abstract":"For first silicon, detection of systematic defects, timing failure and other errors is an extremely time-pressured task because detection and debugging of such failures determines how fast a product can go into mass production. In this paper we describe a new method for this purpose using an event tester. This method allows testing in the same environment as used for the original simulation in which the chip was designed. The method uses original design simulation data directly from the Verilog/VHDL simulation in the VCD format and thus, eliminates test program generation and test vector translation processes into WGL/STIL or ATE formats. It essentially extends the EDA design environment to the physical testing of an IC.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181699
Tomoo Inoue, T. Miura, A. Tamura, H. Fujiwara
Acyclic partial scan design is an efficient DFT method. This paper presents a scheduling method for reducing the number of scan registers for an acyclic structure. In order to estimate the number of scan registers during scheduling, we propose provisional binding of operational units, and show a force-directed scheduling algorithm with the provisional binding. Experimental results show that the number of scan registers in the resulting RTL datapaths can be reduced by our method combined with the binding algorithm for acyclic partial scan.
{"title":"A scheduling method in high-level synthesis for acyclic partial scan design","authors":"Tomoo Inoue, T. Miura, A. Tamura, H. Fujiwara","doi":"10.1109/ATS.2002.1181699","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181699","url":null,"abstract":"Acyclic partial scan design is an efficient DFT method. This paper presents a scheduling method for reducing the number of scan registers for an acyclic structure. In order to estimate the number of scan registers during scheduling, we propose provisional binding of operational units, and show a force-directed scheduling algorithm with the provisional binding. Experimental results show that the number of scan registers in the resulting RTL datapaths can be reduced by our method combined with the binding algorithm for acyclic partial scan.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181716
Shyue-Kung Lu, Chien-Hung Yeh
In this paper, we first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. Based on them, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is used to bypass the faulty cell and the testable/fault-tolerant FFT networks are constructed. Special cell designs are presented which implement the reconfiguration mechanism. The reliability of the FFT system increases significantly. The chip design for the bit-level butterfly module is presented. The hardware overhead is low - about 12% for the bit-level design. For the module-level design, it leads to a lower hardware overhead (about 1/2N, where N is the computation point).
{"title":"Easily testable and fault-tolerant design of FFT butterfly networks","authors":"Shyue-Kung Lu, Chien-Hung Yeh","doi":"10.1109/ATS.2002.1181716","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181716","url":null,"abstract":"In this paper, we first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. Based on them, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is used to bypass the faulty cell and the testable/fault-tolerant FFT networks are constructed. Special cell designs are presented which implement the reconfiguration mechanism. The reliability of the FFT system increases significantly. The chip design for the bit-level butterfly module is presented. The hardware overhead is low - about 12% for the bit-level design. For the module-level design, it leads to a lower hardware overhead (about 1/2N, where N is the computation point).","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127336712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181740
S. Mirkhani, Meisam Lavasani, Z. Navabi
This paper presents a fault simulation environment that takes advantage of available models at the behavioral and gate levels of abstraction. The simulation takes place in VHDL and for fault simulation, special VHDL models are written that are capable of propagating circuit faults. Behavioral VHDL models propagate fault effects that appear on their input ports; in addition to this, gate level VHDL models are capable of injecting faults on their output lines. The fault simulation environment assumes the existence of the gate level and behavioral models for every component, and uses the appropriate model depending on whether a fault belongs to it or another component. A wrapper simulation model that encloses both models of a component switches automatically between the models. The wrapper takes care of feedback in the sequential circuits by always selecting the gate level of a component for propagating its own faults. This environment fits well with the hardware description language settings in which pre-synthesis behavioral models, post-synthesis gate-level models and a mixed simulation environment are available. The paper shows a mathematical analysis illustrating the performance improvement of this method over the traditional gate-level fault simulation.
{"title":"Hierarchical fault simulation using behavioral and gate level hardware models","authors":"S. Mirkhani, Meisam Lavasani, Z. Navabi","doi":"10.1109/ATS.2002.1181740","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181740","url":null,"abstract":"This paper presents a fault simulation environment that takes advantage of available models at the behavioral and gate levels of abstraction. The simulation takes place in VHDL and for fault simulation, special VHDL models are written that are capable of propagating circuit faults. Behavioral VHDL models propagate fault effects that appear on their input ports; in addition to this, gate level VHDL models are capable of injecting faults on their output lines. The fault simulation environment assumes the existence of the gate level and behavioral models for every component, and uses the appropriate model depending on whether a fault belongs to it or another component. A wrapper simulation model that encloses both models of a component switches automatically between the models. The wrapper takes care of feedback in the sequential circuits by always selecting the gate level of a component for propagating its own faults. This environment fits well with the hardware description language settings in which pre-synthesis behavioral models, post-synthesis gate-level models and a mixed simulation environment are available. The paper shows a mathematical analysis illustrating the performance improvement of this method over the traditional gate-level fault simulation.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126352682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181686
I. Pomeranz, S. Reddy
Chronological order enumeration is a static compaction procedure for synchronous sequential circuits that to-date produces the shortest test sequences overall for benchmark circuits. The chronological order enumeration procedure was not meant to compete in computational complexity with the highly-efficient restoration based compaction procedure. Rather, it was developed so as to provide a more aggressive target for static and dynamic test compaction procedures. Nevertheless, we describe in this work several algorithmic methods to improve the efficiency of compaction based on chronological order enumeration. These improvements reduce the run time of chronological order enumeration significantly using the same basic implementation. With these improvements, chronological order enumeration is shown to be faster and more effective than restoration based compaction for sequences produced by an ATPG that already uses restoration based compaction as part of the test generation process. For uncompacted sequences, restoration based compaction followed by the improved chronological order enumeration process is shown to be an effective combination.
{"title":"Improving the efficiency of static compaction based on chronological order enumeration of test sequences [logic testing]","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2002.1181686","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181686","url":null,"abstract":"Chronological order enumeration is a static compaction procedure for synchronous sequential circuits that to-date produces the shortest test sequences overall for benchmark circuits. The chronological order enumeration procedure was not meant to compete in computational complexity with the highly-efficient restoration based compaction procedure. Rather, it was developed so as to provide a more aggressive target for static and dynamic test compaction procedures. Nevertheless, we describe in this work several algorithmic methods to improve the efficiency of compaction based on chronological order enumeration. These improvements reduce the run time of chronological order enumeration significantly using the same basic implementation. With these improvements, chronological order enumeration is shown to be faster and more effective than restoration based compaction for sequences produced by an ATPG that already uses restoration based compaction as part of the test generation process. For uncompacted sequences, restoration based compaction followed by the improved chronological order enumeration process is shown to be an effective combination.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"76 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181717
Shyue-Kung Lu, Chung-Yang Chen
In this paper, we present a novel fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. The input patterns can be easily generated with a k-bit binary counter. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. To locate a faulty CLB (configurable logic block), two diagnosis sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable with our approach.
{"title":"Fault detection and fault diagnosis techniques for lookup table FPGAs","authors":"Shyue-Kung Lu, Chung-Yang Chen","doi":"10.1109/ATS.2002.1181717","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181717","url":null,"abstract":"In this paper, we present a novel fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. The input patterns can be easily generated with a k-bit binary counter. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. To locate a faulty CLB (configurable logic block), two diagnosis sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable with our approach.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116923625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181735
Jaehoon Song, Sungju Park
For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.
{"title":"A simple wrapped core linking module for SoC test access","authors":"Jaehoon Song, Sungju Park","doi":"10.1109/ATS.2002.1181735","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181735","url":null,"abstract":"For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121716331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-18DOI: 10.1109/ATS.2002.1181720
A. Dmitriev, M. Gössel, K. Chakrabarty
Presents the design of robust space compactors for reducing test data volume. These compactors are totally error-propagating for a given test test set, i.e. all possible errors are propagated irrespective of the fault model. In addition, these compactors also provide a high degree of error propagation for other test sets. All errors that affect up to three outputs of the circuit under test, as well as all errors that affect an odd number of outputs, are detected. This is irrespective of the test set or the fault model. The number of compactor outputs grows very slowly with the number of circuit outputs and size of the test set. Finally, no structural information of the circuit under test is required for fault simulation. We present experimental results on compactor design for a set of ISCAS and ITC-99 benchmark circuits.
{"title":"Robust space compaction of test responses","authors":"A. Dmitriev, M. Gössel, K. Chakrabarty","doi":"10.1109/ATS.2002.1181720","DOIUrl":"https://doi.org/10.1109/ATS.2002.1181720","url":null,"abstract":"Presents the design of robust space compactors for reducing test data volume. These compactors are totally error-propagating for a given test test set, i.e. all possible errors are propagated irrespective of the fault model. In addition, these compactors also provide a high degree of error propagation for other test sets. All errors that affect up to three outputs of the circuit under test, as well as all errors that affect an odd number of outputs, are detected. This is irrespective of the test set or the fault model. The number of compactor outputs grows very slowly with the number of circuit outputs and size of the test set. Finally, no structural information of the circuit under test is required for fault simulation. We present experimental results on compactor design for a set of ISCAS and ITC-99 benchmark circuits.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122874809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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