Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988901
M. Tao, Maojun Wang, C. Wen, Jinyan Wang, Y. Hao, Wengang Wu, K. Cheng, B. Shen
This work reports a kilovolt and low current collapse normally-off GaN MOSHEMT on silicon substrate. The device with a drift length of 3 μm features a threshold voltage of 1.7 V and an output current of 430 mA/mm at 8 V gate bias. The off-state breakdown voltage (BV) is as high as 1021 V (800 V) defined at a drain leakage criterion of 10 μA/mm with floating (grounded) substrate. The corresponding breakdown electric field is 3.4 MV/cm and the Baliga's figure-of-merit (BFOM) is 1.6 GW/cm2. A small degradation of the dynamic on-resistance (Ron, d) about 30% is observed with a short pulse width of 500 ns and a quiescent drain bias of 60 V. The record value is supposed to benefit from the intrinsic step-graded field plate, high quality LPCVD SÌ3N4 passivation and material optimization of 4.5 μm thick epitaxial layer.
{"title":"Kilovolt GaN MOSHEMT on silicon substrate with breakdown electric field close to the theoretical limit","authors":"M. Tao, Maojun Wang, C. Wen, Jinyan Wang, Y. Hao, Wengang Wu, K. Cheng, B. Shen","doi":"10.23919/ISPSD.2017.7988901","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988901","url":null,"abstract":"This work reports a kilovolt and low current collapse normally-off GaN MOSHEMT on silicon substrate. The device with a drift length of 3 μm features a threshold voltage of 1.7 V and an output current of 430 mA/mm at 8 V gate bias. The off-state breakdown voltage (BV) is as high as 1021 V (800 V) defined at a drain leakage criterion of 10 μA/mm with floating (grounded) substrate. The corresponding breakdown electric field is 3.4 MV/cm and the Baliga's figure-of-merit (BFOM) is 1.6 GW/cm2. A small degradation of the dynamic on-resistance (Ron, d) about 30% is observed with a short pulse width of 500 ns and a quiescent drain bias of 60 V. The record value is supposed to benefit from the intrinsic step-graded field plate, high quality LPCVD SÌ3N4 passivation and material optimization of 4.5 μm thick epitaxial layer.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128517124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988927
K. Watanabe, M. Nozaki, T. Yamada, S. Nakazawa, Y. Anda, M. Isliida, T. Ueda, A. Yoshigoe, T. Hosoi, T. Shimura, H. Watanabe
We have demonstrated hysteresis-free recessed gate AlGaN/GaN metal-oxide-semiconductor heterojunction field-effect transistor (MOS-HFET) by implementing AIGN gate insulator and selective AlGaN regrowth technique. High thermal stability and excellent electrical properties of AIGN gate dielectrics will provide a large process window for further optimization of AlGaN/GaN MOS-HFET.
{"title":"Design and control of interface reaction between Al-based dielectrics and AlGaN layer for hysteresis-free AlGaN/GaN MOS-HFETs","authors":"K. Watanabe, M. Nozaki, T. Yamada, S. Nakazawa, Y. Anda, M. Isliida, T. Ueda, A. Yoshigoe, T. Hosoi, T. Shimura, H. Watanabe","doi":"10.23919/ISPSD.2017.7988927","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988927","url":null,"abstract":"We have demonstrated hysteresis-free recessed gate AlGaN/GaN metal-oxide-semiconductor heterojunction field-effect transistor (MOS-HFET) by implementing AIGN gate insulator and selective AlGaN regrowth technique. High thermal stability and excellent electrical properties of AIGN gate dielectrics will provide a large process window for further optimization of AlGaN/GaN MOS-HFET.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"9 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988900
M. Hua, Zhaofu Zhang, Qingkai Qian, Jin Wei, Qilong Bao, Gaofei Tang, K. J. Chen
In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ∼ 780 °C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).
{"title":"High-performance fully-recessed enhancement-mode GaN MIS-FETs with crystalline oxide interlayer","authors":"M. Hua, Zhaofu Zhang, Qingkai Qian, Jin Wei, Qilong Bao, Gaofei Tang, K. J. Chen","doi":"10.23919/ISPSD.2017.7988900","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988900","url":null,"abstract":"In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ∼ 780 °C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121866189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988888
K. Kawahara, S. Hino, K. Sadamatsu, Y. Nakao, Yusuke Yamashiro, Yasuki Yamamoto, T. Iwamatsu, S. Nakata, S. Tomohisa, S. Yamakawa
For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.
{"title":"6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module","authors":"K. Kawahara, S. Hino, K. Sadamatsu, Y. Nakao, Yusuke Yamashiro, Yasuki Yamamoto, T. Iwamatsu, S. Nakata, S. Tomohisa, S. Yamakawa","doi":"10.23919/ISPSD.2017.7988888","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988888","url":null,"abstract":"For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122177242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988953
M. Qiao, Zhengkang Wang, Huihui Wang, Feng Jin, Zhaoji Li, Bo Zhang
This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters LP and L2 in the layout of the transition region of the edge termination were studied by 3-D numerical simulations and experiments to overcome these issues. As implantation dose of n-top layer (Dntop) increases from 0.8 × cm−2 to 1.2 × cm−2, progressive performance with Fß from 805 V to 711 V and Ron, sp from 86.49 mΩ· cm2 to 80.56 mΩ·cm2 is experimental obtained and the novel LDMOS demonstrates maximum figure of merit (FOM) in the latest existing 700-V LDMOS technologies.
{"title":"Edge termination design of a 700-V triple RESURF LDMOS with n-type top layer","authors":"M. Qiao, Zhengkang Wang, Huihui Wang, Feng Jin, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988953","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988953","url":null,"abstract":"This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters L<inf>P</inf> and L<inf>2</inf> in the layout of the transition region of the edge termination were studied by 3-D numerical simulations and experiments to overcome these issues. As implantation dose of n-top layer (D<inf>ntop</inf>) increases from 0.8 × cm<sup>−2</sup> to 1.2 × cm<sup>−2</sup>, progressive performance with Fß from 805 V to 711 V and R<inf>on, sp</inf> from 86.49 mΩ· cm<sup>2</sup> to 80.56 mΩ·cm<sup>2</sup> is experimental obtained and the novel LDMOS demonstrates maximum figure of merit (FOM) in the latest existing 700-V LDMOS technologies.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125990359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988965
K. Hara, Tomoko Kakegawa, S. Wada, Tomoyuki Utsumi, T. Oda
We have proposed the concept of thin layer SOI devices with stepped field plates to obtain a low on-resistance LDMOSFET. Thin layer SOI devices can acquire a high breakdown voltage because the ionization integral over the vertical path may be neglected. A doping concentration in a drift region of a thin layer SOI device can be increased by reducing the thickness of the surface oxide. This is because the amount of induced charge increases by reducing the thickness of the oxide. The 600-V LDMOSFET was fabricated in line with the proposed concept and it accomplished the best trade-off among the LDMOSFETs reported so far (the breakdown voltage of 645 V and the specific on-resistance of 4.5 Ω·mm2).
我们提出了采用阶梯场板的薄层SOI器件的概念，以获得低导通电阻的LDMOSFET。由于可以忽略垂直路径上的电离积分，薄层SOI器件可以获得高击穿电压。通过减小表面氧化物的厚度，可以增加薄层SOI器件漂移区的掺杂浓度。这是因为随着氧化物厚度的减小，诱导电荷的数量增加了。600 V LDMOSFET的制造符合所提出的概念，它完成了迄今为止报道的LDMOSFET的最佳权衡(击穿电压为645 V，比导通电阻为4.5 Ω·mm2)。
{"title":"Low on-resistance high voltage thin layer SOI LDMOS transistors with stepped field plates","authors":"K. Hara, Tomoko Kakegawa, S. Wada, Tomoyuki Utsumi, T. Oda","doi":"10.23919/ISPSD.2017.7988965","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988965","url":null,"abstract":"We have proposed the concept of thin layer SOI devices with stepped field plates to obtain a low on-resistance LDMOSFET. Thin layer SOI devices can acquire a high breakdown voltage because the ionization integral over the vertical path may be neglected. A doping concentration in a drift region of a thin layer SOI device can be increased by reducing the thickness of the surface oxide. This is because the amount of induced charge increases by reducing the thickness of the oxide. The 600-V LDMOSFET was fabricated in line with the proposed concept and it accomplished the best trade-off among the LDMOSFETs reported so far (the breakdown voltage of 645 V and the specific on-resistance of 4.5 Ω·mm2).","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988892
Y. Takeuchi, T. Miyoshi, T. Furukawa, M. Shiraishi, M. Mori
In this paper, a novel hybrid power module using a new combination of dual side-gate HiGTs (high-conductivity IGBT) and SiC-SBDs is proposed. This combination achieves drastic switching loss reductions at a turn-off loss of −43%, a turn-on loss of −71%, and a reverse recovery loss of −98% compared with a conventional combination of trench gate HiGTs and U-SFDs (ultra soft & fast recovery diode). As a result, the proposed DuSH module (dual side-gate HiGT hybrid module) has an extremely low inverter loss of −50%, similar to SiC-MOSFETs.
{"title":"A novel hybrid power module with dual side-gate HiGT and SiC-SBD","authors":"Y. Takeuchi, T. Miyoshi, T. Furukawa, M. Shiraishi, M. Mori","doi":"10.23919/ISPSD.2017.7988892","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988892","url":null,"abstract":"In this paper, a novel hybrid power module using a new combination of dual side-gate HiGTs (high-conductivity IGBT) and SiC-SBDs is proposed. This combination achieves drastic switching loss reductions at a turn-off loss of −43%, a turn-on loss of −71%, and a reverse recovery loss of −98% compared with a conventional combination of trench gate HiGTs and U-SFDs (ultra soft & fast recovery diode). As a result, the proposed DuSH module (dual side-gate HiGT hybrid module) has an extremely low inverter loss of −50%, similar to SiC-MOSFETs.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127091547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988912
B. Vogler, R. Herzer, Markus Dienstbier, S. Buetow
A new gate driver IC in SOI technology is presented which integrates all primary and secondary side driver functions for a three-phase MOSFET power inverter system and with brake chopper on a single chip. Thanks to the used SOI technology which blocks voltages in both directions an unique property of the IC is the potential separation for each secondary side thus allowing a decoupling from the primary side as known from solutions with galvanic isolation. For control and fault signal transmission advanced level shifter circuits are used. The IC furthermore includes short circuit protection (VDS-monitoring for each switch), operation voltage monitoring and advanced error management with detailed error read-out. The presented static and dynamic measurement results demonstrate the driver performance and the regular operation in the inverter system.
{"title":"Fully integrated high voltage high current gate driver for MOSFET-inverters","authors":"B. Vogler, R. Herzer, Markus Dienstbier, S. Buetow","doi":"10.23919/ISPSD.2017.7988912","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988912","url":null,"abstract":"A new gate driver IC in SOI technology is presented which integrates all primary and secondary side driver functions for a three-phase MOSFET power inverter system and with brake chopper on a single chip. Thanks to the used SOI technology which blocks voltages in both directions an unique property of the IC is the potential separation for each secondary side thus allowing a decoupling from the primary side as known from solutions with galvanic isolation. For control and fault signal transmission advanced level shifter circuits are used. The IC furthermore includes short circuit protection (VDS-monitoring for each switch), operation voltage monitoring and advanced error management with detailed error read-out. The presented static and dynamic measurement results demonstrate the driver performance and the regular operation in the inverter system.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124450406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988961
Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Desheng Ding, Yan Gu, Sen Zhang, Bo Hou
This paper proposes a 500V U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to improve the trade-off between the saturation voltage (VCEsat) and the turn-off loss (Eoff). The proposed dual trenches U-shaped channel (DTU) SOI-LIGBT features a U-shaped gate trench (Gl) and a U-shaped hole barrier trench (G2). By employing the dual trenches, enhanced carrier stored effect at the emitter side and more uniform carriers distribution in the drift region can be obtained, resulting in decreases of VCEsat and Eoff. By optimizing the dimensions of the U-shaped channel, it is found that the proposed DTU SOI-LIGBT can achieve a 52.3% lower Eoff compared with the planar gate U-shaped channel (PGU) SOI-LIGBT at the same VCEsat of 1.22 V.
本文提出了一种500V u型沟道绝缘体上硅侧绝缘栅双极晶体管(soi - light)，具有双沟槽，以改善饱和电压(VCEsat)和关断损耗(Eoff)之间的权衡。所提出的双沟槽u形通道(DTU) soi - light具有u形栅极沟槽(Gl)和u形孔阻挡沟槽(G2)。采用双沟槽可以增强发射极侧载流子的存储效应，使漂移区载流子分布更加均匀，从而降低了VCEsat和Eoff。通过优化u型沟道的尺寸，发现在相同电压电压为1.22 V时，所提出的DTU soi - light与平面栅极u型沟道(PGU) soi - light相比，Eoff降低了52.3%。
{"title":"U-shaped channel SOI-LIGBT with dual trenches to improve the trade-off between saturation voltage and turn-off loss","authors":"Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Desheng Ding, Yan Gu, Sen Zhang, Bo Hou","doi":"10.23919/ISPSD.2017.7988961","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988961","url":null,"abstract":"This paper proposes a 500V U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to improve the trade-off between the saturation voltage (VCEsat) and the turn-off loss (Eoff). The proposed dual trenches U-shaped channel (DTU) SOI-LIGBT features a U-shaped gate trench (Gl) and a U-shaped hole barrier trench (G2). By employing the dual trenches, enhanced carrier stored effect at the emitter side and more uniform carriers distribution in the drift region can be obtained, resulting in decreases of VCEsat and Eoff. By optimizing the dimensions of the U-shaped channel, it is found that the proposed DTU SOI-LIGBT can achieve a 52.3% lower Eoff compared with the planar gate U-shaped channel (PGU) SOI-LIGBT at the same VCEsat of 1.22 V.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988878
T. Mori, H. Fujii, Shunji Kubo, T. Ipposhi
In this paper, we propose a Split-Recessed-Gate LDMOS (SRG-LDMOS) which minimizes HCl degradation with negligible increase in specific on-resistance. In SRG-LDMOS structure, the gate poly is split into two parts, the primal gate on the channel and the secondary recessed gate on the STI. This secondary recessed gate is nominally connected to source to minimize the HCl degradation although it is possible to be biased independently. The recessed gate connected to source helps to relax the electric field and decrease the impact ionization generation rate near the channel-side STI edge during the HCl stress.
{"title":"Investigation into HCl improvement by a split-reeessed-gate structure in an STI-based nLDMOSFET","authors":"T. Mori, H. Fujii, Shunji Kubo, T. Ipposhi","doi":"10.23919/ISPSD.2017.7988878","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988878","url":null,"abstract":"In this paper, we propose a Split-Recessed-Gate LDMOS (SRG-LDMOS) which minimizes HCl degradation with negligible increase in specific on-resistance. In SRG-LDMOS structure, the gate poly is split into two parts, the primal gate on the channel and the secondary recessed gate on the STI. This secondary recessed gate is nominally connected to source to minimize the HCl degradation although it is possible to be biased independently. The recessed gate connected to source helps to relax the electric field and decrease the impact ionization generation rate near the channel-side STI edge during the HCl stress.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122942253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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