Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569596
Sushmit Goswami, Helen Kim, J. Dawson
A tunable and highly digital RF frontend for multi-band TDD radios is integrated in 45nm SOI CMOS. The PA absorbs the TX branch of the TX/RX switch with no added loss. Peak PA output power is 27.5±0.5dBm from 1.6 to 3.4GHz, with up to 30% total efficiency at 2V. For TDD LTE applications, better than -30dBc ACLR and -25dB EVM is measured with 16-QAM, 20MHz signals from 1.65 to 3.5GHz, with up to 16.5% average efficiency and 22.9dBm average power. The broadband LNA achieves AV > 14dB, NF=4.3 ± 1.6dB and IIP3 > -7dBm from 1.6 to 3.4GHz while drawing just 6mA from 1V.
{"title":"A frequency-agile RF frontend for multi-band TDD radios in 45nm SOI CMOS","authors":"Sushmit Goswami, Helen Kim, J. Dawson","doi":"10.1109/RFIC.2013.6569596","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569596","url":null,"abstract":"A tunable and highly digital RF frontend for multi-band TDD radios is integrated in 45nm SOI CMOS. The PA absorbs the TX branch of the TX/RX switch with no added loss. Peak PA output power is 27.5±0.5dBm from 1.6 to 3.4GHz, with up to 30% total efficiency at 2V. For TDD LTE applications, better than -30dBc ACLR and -25dB EVM is measured with 16-QAM, 20MHz signals from 1.65 to 3.5GHz, with up to 16.5% average efficiency and 22.9dBm average power. The broadband LNA achieves AV > 14dB, NF=4.3 ± 1.6dB and IIP3 > -7dBm from 1.6 to 3.4GHz while drawing just 6mA from 1V.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115761702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569538
Ye Zhang, Lei Liao, M. Wei, Jan Henning Mueller, B. Mohr, A. Atac, Yifan Wang, M. Schleyer, R. Wunderlich, R. Negra, S. Heinen
This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.
{"title":"A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump","authors":"Ye Zhang, Lei Liao, M. Wei, Jan Henning Mueller, B. Mohr, A. Atac, Yifan Wang, M. Schleyer, R. Wunderlich, R. Negra, S. Heinen","doi":"10.1109/RFIC.2013.6569538","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569538","url":null,"abstract":"This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116256852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569601
J. Curtis, A. Pham, M. Chirala, F. Aryanfar, Zhouyue Pi
We present the design and development of the first fully integrated, two stage Doherty power amplifier (DPA) in the Ka-Band. The DPA is fabricated in a 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. At 26.4 GHz, the amplifier achieves measured small signal gain of 10.3 dB, output power at 1-dB compression point (P1dB) of 25.1 dBm, peak power added efficiency (PAE) of 38%, and PAE of 27% at 6 dB back-off power. To the best of the author's knowledge, this Doherty circuit is the first fully integrated millimeter-wave amplifier that achieves the highest power and a recorded 27% PAE at 6-dB back-off and each unit amplifier has 2 stages.
{"title":"A Ka-Band doherty power amplifier with 25.1 dBm output power, 38% peak PAE and 27% back-off PAE","authors":"J. Curtis, A. Pham, M. Chirala, F. Aryanfar, Zhouyue Pi","doi":"10.1109/RFIC.2013.6569601","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569601","url":null,"abstract":"We present the design and development of the first fully integrated, two stage Doherty power amplifier (DPA) in the Ka-Band. The DPA is fabricated in a 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. At 26.4 GHz, the amplifier achieves measured small signal gain of 10.3 dB, output power at 1-dB compression point (P1dB) of 25.1 dBm, peak power added efficiency (PAE) of 38%, and PAE of 27% at 6 dB back-off power. To the best of the author's knowledge, this Doherty circuit is the first fully integrated millimeter-wave amplifier that achieves the highest power and a recorded 27% PAE at 6-dB back-off and each unit amplifier has 2 stages.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114199756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569616
Hao Gao, M. Matters-Kammerer, P. Harpe, D. Milosevic, U. Johannsen, A. V. van Roermund, P. Baltus
This paper presents the first monolithically integrated RF-power harvesting 71 GHz wireless temperature sensor node in 65nm CMOS technology, containing a monopole antenna, a 71 GHz RF power harvesting unit with storage capacitor array, an End-of-Burst monitor, a temperature sensor and an ultra-low-power transmitter at 79 GHz. At 71 GHz, the RF to DC converter achieves a power conversion efficiency of 8% for 5 dBm input power.
{"title":"A 71GHz RF energy harvesting tag with 8% efficiency for wireless temperature sensors in 65nm CMOS","authors":"Hao Gao, M. Matters-Kammerer, P. Harpe, D. Milosevic, U. Johannsen, A. V. van Roermund, P. Baltus","doi":"10.1109/RFIC.2013.6569616","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569616","url":null,"abstract":"This paper presents the first monolithically integrated RF-power harvesting 71 GHz wireless temperature sensor node in 65nm CMOS technology, containing a monopole antenna, a 71 GHz RF power harvesting unit with storage capacitor array, an End-of-Burst monitor, a temperature sensor and an ultra-low-power transmitter at 79 GHz. At 71 GHz, the RF to DC converter achieves a power conversion efficiency of 8% for 5 dBm input power.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569527
Jaesik Lee, Inseop Lee, Jubong Park, Junho Moon, Seungsoo Kim, Jaeyoung Lee
A fully integrated low-power sub-GHz sensor node is presented for wireless sensor networks (WSN). The sensor node features a sensor IC and a RF transceiver IC, vertically assembled in a single QFN package. A unique remote power-up scheme is configured to supply the power to a sensor node from power-down state. It features a technique of centralized remote power-up scheme combined with local broadcasting power-up sequence to achieve ultra-low standby current, fast power-up time, and extended coverage. It proposes a time division switch to separate power-up message from data information, both propagated at the same frequency band. The standby current in power-down state draws less than 450nA. The sensitivity of power-up receiver is -24dBm, while the sensitivity of data receiver is -103dBm. The Sensor and RF transceiver ICs were fabricated in 0.25μm CMOS and 0.18μm RF CMOS, respectively.
{"title":"A sub-GHz low-power wireless sensor node with remote power-up receiver","authors":"Jaesik Lee, Inseop Lee, Jubong Park, Junho Moon, Seungsoo Kim, Jaeyoung Lee","doi":"10.1109/RFIC.2013.6569527","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569527","url":null,"abstract":"A fully integrated low-power sub-GHz sensor node is presented for wireless sensor networks (WSN). The sensor node features a sensor IC and a RF transceiver IC, vertically assembled in a single QFN package. A unique remote power-up scheme is configured to supply the power to a sensor node from power-down state. It features a technique of centralized remote power-up scheme combined with local broadcasting power-up sequence to achieve ultra-low standby current, fast power-up time, and extended coverage. It proposes a time division switch to separate power-up message from data information, both propagated at the same frequency band. The standby current in power-down state draws less than 450nA. The sensitivity of power-up receiver is -24dBm, while the sensitivity of data receiver is -103dBm. The Sensor and RF transceiver ICs were fabricated in 0.25μm CMOS and 0.18μm RF CMOS, respectively.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569524
K. Natarajan, Daibashish Gangopadhyay, D. Allstot
An RF transmitter that uses closed-loop PLL-based BFSK modulation and is reconfigurable for both the MedRadio (402-405MHz) and 433 MHz ISM bands is introduced. Innovations include the first reconfigurable class-C PA, the first class-C PA with automatic calibration against PVT variations, and a low-power NMOS delay-based ring-VCO PLL. Several performance records are achieved: (1) The PA realizes a peak efficiency of 47% in the high-power (ISM) (-2 dBm) mode and 43% (33%) in the MedRadio -12 dBm (-16 dBm backoff) modes. (2) The PLL dissipates only 72 μW with a phase noise of-111 dBc/Hz @ 1 MHz, and (3) the overall transmit efficiencies are 29% and 17% for the -12 dBm and -16 dBm backoff levels for the MedRadio band and 44% for the ISM (433 MHz) bands.
{"title":"A PLL-based BFSK transmitter with reconfigurable and PVT-tolerant class-C PA for medradio & ISM (433MHz) standards","authors":"K. Natarajan, Daibashish Gangopadhyay, D. Allstot","doi":"10.1109/RFIC.2013.6569524","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569524","url":null,"abstract":"An RF transmitter that uses closed-loop PLL-based BFSK modulation and is reconfigurable for both the MedRadio (402-405MHz) and 433 MHz ISM bands is introduced. Innovations include the first reconfigurable class-C PA, the first class-C PA with automatic calibration against PVT variations, and a low-power NMOS delay-based ring-VCO PLL. Several performance records are achieved: (1) The PA realizes a peak efficiency of 47% in the high-power (ISM) (-2 dBm) mode and 43% (33%) in the MedRadio -12 dBm (-16 dBm backoff) modes. (2) The PLL dissipates only 72 μW with a phase noise of-111 dBc/Hz @ 1 MHz, and (3) the overall transmit efficiencies are 29% and 17% for the -12 dBm and -16 dBm backoff levels for the MedRadio band and 44% for the ISM (433 MHz) bands.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569548
Peyman Nazari, Byung-Kwan Chun, Vipul Kumar, Eric Middleton, Z. Wang, P. Heydari
A polar quantizer is presented for detection and quantization of modulated signals in cellular applications. It consists of amplitude and phase quantizers. A time-to-digital converter (TDC) is designed to measure and quantize the phase, while a typical ADC is used for amplitude quantization. Polar quantizer significantly reduces the sensitivity of the quantizer to amplitude resolution. The 10 bit polar quantizer fabricated in 130nm CMOS achieves 5.5dB of SQNR improvement compared to rectangular quantizer for signal bandwidths as high as 20MHz.
{"title":"A 130nm CMOS polar quantizer for cellular applications","authors":"Peyman Nazari, Byung-Kwan Chun, Vipul Kumar, Eric Middleton, Z. Wang, P. Heydari","doi":"10.1109/RFIC.2013.6569548","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569548","url":null,"abstract":"A polar quantizer is presented for detection and quantization of modulated signals in cellular applications. It consists of amplitude and phase quantizers. A time-to-digital converter (TDC) is designed to measure and quantize the phase, while a typical ADC is used for amplitude quantization. Polar quantizer significantly reduces the sensitivity of the quantizer to amplitude resolution. The 10 bit polar quantizer fabricated in 130nm CMOS achieves 5.5dB of SQNR improvement compared to rectangular quantizer for signal bandwidths as high as 20MHz.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"18 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569617
M. Nariman, Farid Shirinfar, S. Pamarti, M. Rofougaran, R. Rofougaran, F. De Flaviis
A compact energy transmission system in 40nm standard CMOS is presented. The system consists of a 60GHz VCO followed by a quad-core power amplifier as transmitter and an RF-to-DC converter as receiver. The total power delivered by the quad-core PA to its four 50Ω loads is 24.6dBm. The receiver is a complementary cross-coupled rectifier with a measured efficiency of 28% while supplying 1mA of current. The system can support amplitude and frequency modulations and beam-forming capabilities for wireless applications with minimal front-end complexities.
{"title":"A compact millimeter-wave energy transmission system for wireless applications","authors":"M. Nariman, Farid Shirinfar, S. Pamarti, M. Rofougaran, R. Rofougaran, F. De Flaviis","doi":"10.1109/RFIC.2013.6569617","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569617","url":null,"abstract":"A compact energy transmission system in 40nm standard CMOS is presented. The system consists of a 60GHz VCO followed by a quad-core power amplifier as transmitter and an RF-to-DC converter as receiver. The total power delivered by the quad-core PA to its four 50Ω loads is 24.6dBm. The receiver is a complementary cross-coupled rectifier with a measured efficiency of 28% while supplying 1mA of current. The system can support amplitude and frequency modulations and beam-forming capabilities for wireless applications with minimal front-end complexities.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"165 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569586
A. Hamidian, R. Ebelt, D. Shmakov, M. Vossiek, Tao Zhang, V. Subramanian, G. Boeck
This paper presents a 130 nm CMOS transceiver for 24 GHz wireless indoor localization. Due to a novel Rx/Tx switching concept RF-losses between receiver/transmitter and antenna could be reduced and the T/R isolation was drastically improved. The measured transceiver chip achieves an output power and noise figure of >5 dBm and <;6 dB, respectively with 2 mm2 total chip size. The complete transceiver consumes 16 mW in the Rxand 26 mW in the Tx-mode. The RF-transceiver-chip was integrated with a DSP-unit and mounted on a PCB for wireless indoor localization demonstration. The measured results show a distance measurement precision in the cm-range.
{"title":"24 GHz CMOS transceiver with novel T/R switching concept for indoor localization","authors":"A. Hamidian, R. Ebelt, D. Shmakov, M. Vossiek, Tao Zhang, V. Subramanian, G. Boeck","doi":"10.1109/RFIC.2013.6569586","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569586","url":null,"abstract":"This paper presents a 130 nm CMOS transceiver for 24 GHz wireless indoor localization. Due to a novel Rx/Tx switching concept RF-losses between receiver/transmitter and antenna could be reduced and the T/R isolation was drastically improved. The measured transceiver chip achieves an output power and noise figure of >5 dBm and <;6 dB, respectively with 2 mm2 total chip size. The complete transceiver consumes 16 mW in the Rxand 26 mW in the Tx-mode. The RF-transceiver-chip was integrated with a DSP-unit and mounted on a PCB for wireless indoor localization demonstration. The measured results show a distance measurement precision in the cm-range.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134482394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569515
T. Siriburanon, W. Deng, K. Okada, A. Matsuzawa
This paper proposes a low-power currentreuse complementary differential LC-VCO which is composed of a pair of NMOS and PMOS transistors with an adaptive bias scheme for both transistors to ensure its robust startup and achieve maximum swing in Class-C operation. The proposed VCO has been implemented in a standard 0.18μm CMOS technology, which oscillates at the carrier frequency of 4.6 GHz. The measured phase noise is -139.5dBc/Hz at 10 MHz offset while drawing a current consumption of 1.6 mA from 1.5 V supply. The Figure of Merit is -189.1 dBc/Hz. To the author's best knowledge, this is the first class-C current-reuse VCO with an adaptive bias scheme.
{"title":"A current-reuse Class-C LC-VCO with an adaptive bias scheme","authors":"T. Siriburanon, W. Deng, K. Okada, A. Matsuzawa","doi":"10.1109/RFIC.2013.6569515","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569515","url":null,"abstract":"This paper proposes a low-power currentreuse complementary differential LC-VCO which is composed of a pair of NMOS and PMOS transistors with an adaptive bias scheme for both transistors to ensure its robust startup and achieve maximum swing in Class-C operation. The proposed VCO has been implemented in a standard 0.18μm CMOS technology, which oscillates at the carrier frequency of 4.6 GHz. The measured phase noise is -139.5dBc/Hz at 10 MHz offset while drawing a current consumption of 1.6 mA from 1.5 V supply. The Figure of Merit is -189.1 dBc/Hz. To the author's best knowledge, this is the first class-C current-reuse VCO with an adaptive bias scheme.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"38 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132605997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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