Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569557
Hao Gao, M. Matters-Kammerer, D. Milosevic, A. V. van Roermund, P. Baltus
This paper presents the first 62 GHz fully onchip RF-DC rectifier in 65nm CMOS technology. The rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, efficiency problems of the mm-wave rectifier are discussed and the inductor-peaked rectifier structure is proposed and realized. By using an inductor-peaked diode connected transistor, self-threshold voltage modulation, and an output filter, the measured rectifier reaches 7% efficiency with 1 mA current load. Compared to previous state-of-art 45 GHz rectifier with 1.2% efficiency [1], our solution achieves a higher efficiency at a higher frequency, providing a better solution for mm-wave wireless power receivers.
{"title":"A 62 GHz inductor-peaked rectifier with 7% efficiency","authors":"Hao Gao, M. Matters-Kammerer, D. Milosevic, A. V. van Roermund, P. Baltus","doi":"10.1109/RFIC.2013.6569557","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569557","url":null,"abstract":"This paper presents the first 62 GHz fully onchip RF-DC rectifier in 65nm CMOS technology. The rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, efficiency problems of the mm-wave rectifier are discussed and the inductor-peaked rectifier structure is proposed and realized. By using an inductor-peaked diode connected transistor, self-threshold voltage modulation, and an output filter, the measured rectifier reaches 7% efficiency with 1 mA current load. Compared to previous state-of-art 45 GHz rectifier with 1.2% efficiency [1], our solution achieves a higher efficiency at a higher frequency, providing a better solution for mm-wave wireless power receivers.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134282353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569621
Chenliang Du, H. Hashemi
This paper presents an integrated UWB shortrange impulse radar implemented in a 130 nm CMOS process. The transmitter can digitally generate various waveforms with up to 10 GHz bandwidth at 5 dBm peak power. The receiver utilizes a time interleaved scheme to support a 20 GS/s effective sampling rate. Sample-domain averaging of multiple identical received waveforms reduces the required digitization rate and corresponding power consumption. Sampling clocks for the time interleaved samplers are generated using independent delay locked loops that are locked to the same reference. Measurement results of the individual blocks as well as the entire system are presented.
{"title":"An UWB CMOS impulse radar","authors":"Chenliang Du, H. Hashemi","doi":"10.1109/RFIC.2013.6569621","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569621","url":null,"abstract":"This paper presents an integrated UWB shortrange impulse radar implemented in a 130 nm CMOS process. The transmitter can digitally generate various waveforms with up to 10 GHz bandwidth at 5 dBm peak power. The receiver utilizes a time interleaved scheme to support a 20 GS/s effective sampling rate. Sample-domain averaging of multiple identical received waveforms reduces the required digitization rate and corresponding power consumption. Sampling clocks for the time interleaved samplers are generated using independent delay locked loops that are locked to the same reference. Measurement results of the individual blocks as well as the entire system are presented.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569520
A. Antonopoulos, M. Bucher, K. Papathanasiou, N. Makris, R. K. Sharma, P. Sakalas, M. Schroter
This work presents an analysis of high frequency noise and linearity performance of a 90 nm CMOS process. Measurements are performed for a wide range of nominal gate lengths and bias points at high frequency. Modeling is based on the EKV3 compact model in Spectre RF circuit simulator from Cadence. The model shows correct scalability for noise and linearity accounting for short channel effects (SCEs), such as velocity saturation (VS) and channel length modulation (CLM). Results are presented versus a common measure of channel inversion level, named inversion coefficient. Optimum performance is shown to gradually shift from higher to lower levels of moderate inversion, when scaling from 240 nm to 100 nm. The same trend is observed from investigating the transconductance frequency product (TFP) of a common-source (CS) LNA for technology nodes ranging from 180 nm to 22 nm.
{"title":"CMOS RF noise, scaling, and compact modeling for RFIC design","authors":"A. Antonopoulos, M. Bucher, K. Papathanasiou, N. Makris, R. K. Sharma, P. Sakalas, M. Schroter","doi":"10.1109/RFIC.2013.6569520","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569520","url":null,"abstract":"This work presents an analysis of high frequency noise and linearity performance of a 90 nm CMOS process. Measurements are performed for a wide range of nominal gate lengths and bias points at high frequency. Modeling is based on the EKV3 compact model in Spectre RF circuit simulator from Cadence. The model shows correct scalability for noise and linearity accounting for short channel effects (SCEs), such as velocity saturation (VS) and channel length modulation (CLM). Results are presented versus a common measure of channel inversion level, named inversion coefficient. Optimum performance is shown to gradually shift from higher to lower levels of moderate inversion, when scaling from 240 nm to 100 nm. The same trend is observed from investigating the transconductance frequency product (TFP) of a common-source (CS) LNA for technology nodes ranging from 180 nm to 22 nm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"99 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128010471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569620
Pieter A. J. Nuyts, P. Reynaert, W. Dehaene
A fully digital 1 to 3 GHz multimode transmitter is presented which contains two RF modulators: One uses baseband (BB) PWM, while the other uses RF PWM. RF PWM produces less harmonics, while BB PWM has a higher dynamic range (DR) and consumes less power. The BB PWM system satisfies the WLAN EVM limit over the whole frequency range. The RF PWM system achieves sufficient EVM for standards such as EDGE and WCDMA. Both systems support the use of multiple PAs to extend the DR using multilevel PWM.
{"title":"A fully digital PWM-based 1 to 3 GHz multistandard transmitter in 40-nm CMOS","authors":"Pieter A. J. Nuyts, P. Reynaert, W. Dehaene","doi":"10.1109/RFIC.2013.6569620","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569620","url":null,"abstract":"A fully digital 1 to 3 GHz multimode transmitter is presented which contains two RF modulators: One uses baseband (BB) PWM, while the other uses RF PWM. RF PWM produces less harmonics, while BB PWM has a higher dynamic range (DR) and consumes less power. The BB PWM system satisfies the WLAN EVM limit over the whole frequency range. The RF PWM system achieves sufficient EVM for standards such as EDGE and WCDMA. Both systems support the use of multiple PAs to extend the DR using multilevel PWM.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569559
M. M. Bajestan, K. Entesari
This paper presents a wide-tuning range Voltage-Controlled Oscillator (VCO) for software-defined radio (SDR) applications using a resonator with three potential oscillation modes. The implemented prototype in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12GHz to 12.95GHz while drawing 5 to 10mA current from 1-V supply. The measured phase noise at 1MHz offset from carrier frequencies of 5.9, 9.12 and 12.25GHz is -122.9, -117.1 and -110.5dBc/Hz, respectively. The VCO occupies a chip area of 0.33mm2.
{"title":"A 5.12–12.95GHz triple-resonance low phase noise CMOS VCO for software-defined radio applications","authors":"M. M. Bajestan, K. Entesari","doi":"10.1109/RFIC.2013.6569559","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569559","url":null,"abstract":"This paper presents a wide-tuning range Voltage-Controlled Oscillator (VCO) for software-defined radio (SDR) applications using a resonator with three potential oscillation modes. The implemented prototype in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12GHz to 12.95GHz while drawing 5 to 10mA current from 1-V supply. The measured phase noise at 1MHz offset from carrier frequencies of 5.9, 9.12 and 12.25GHz is -122.9, -117.1 and -110.5dBc/Hz, respectively. The VCO occupies a chip area of 0.33mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569567
Yanjie Wang, C. Hull, Glenn Murata, S. Ravid
This paper presents an analog baseband (ABB) circuit for low power 60 GHz wireless receiver in standard 65 nm CMOS. The proposed analog baseband system combines variable gain amplifiers (VGA) with a 3rd-order type II Chebyshev filter and provides linear steps as well as filter tuning range to achieve sufficient out-of-band rejection. The ABB demonstrates 2 dB gain step tuning range from 3 - 31 dB, 3-dB bandwidth of 980 MHz, OP1dB of 0dBm, and noise figure of 6 dB to 21 dB. The ABB consumes 48 mW at max gain setting and 32 mW at minimum gain setting from a 1.1 V supply. The entire ABB occupies an area of 1.1 mm2 with active area of 0.2 mm2.
{"title":"A linear-in-dB analog baseband circuit for low power 60GHz receiver in standard 65nm CMOS","authors":"Yanjie Wang, C. Hull, Glenn Murata, S. Ravid","doi":"10.1109/RFIC.2013.6569567","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569567","url":null,"abstract":"This paper presents an analog baseband (ABB) circuit for low power 60 GHz wireless receiver in standard 65 nm CMOS. The proposed analog baseband system combines variable gain amplifiers (VGA) with a 3rd-order type II Chebyshev filter and provides linear steps as well as filter tuning range to achieve sufficient out-of-band rejection. The ABB demonstrates 2 dB gain step tuning range from 3 - 31 dB, 3-dB bandwidth of 980 MHz, OP1dB of 0dBm, and noise figure of 6 dB to 21 dB. The ABB consumes 48 mW at max gain setting and 32 mW at minimum gain setting from a 1.1 V supply. The entire ABB occupies an area of 1.1 mm2 with active area of 0.2 mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569614
F. Nakazawa, T. Shimanouchi, T. Katsuki, O. Toyoda, S. Ueda
This paper describes a novel design of a MEMS variable capacitor with high operating reliability and high quality factor. Metal-Insulator-Metal (MIM) dots between a fixed electrode and a movable electrode in a variable capacitor is proposed. A Fabricated MEMS capacitor was operated one billion or more times without sticking. It demonstrated a high quality factor of 200 at 0.5 pF. It was experimentally confirmed that MIM dots effectively achieve a sticking-free and high-quality-factor MEMS variable capacitor.
{"title":"A sticking-free and high-quality factor MEMS variable capacitor with metal-insulator-metal dots as dielectric layer","authors":"F. Nakazawa, T. Shimanouchi, T. Katsuki, O. Toyoda, S. Ueda","doi":"10.1109/RFIC.2013.6569614","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569614","url":null,"abstract":"This paper describes a novel design of a MEMS variable capacitor with high operating reliability and high quality factor. Metal-Insulator-Metal (MIM) dots between a fixed electrode and a movable electrode in a variable capacitor is proposed. A Fabricated MEMS capacitor was operated one billion or more times without sticking. It demonstrated a high quality factor of 200 at 0.5 pF. It was experimentally confirmed that MIM dots effectively achieve a sticking-free and high-quality-factor MEMS variable capacitor.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569532
N. Khanh, K. Asada
This paper presents a leakage cancellation technique for on-chip transceiver for range sensing radar. A 180-nm CMOS transceiver with on-chip antennas is implemented with a 9-11-GHz damping-pulse transmitter (Tx) and a receiver (Rx) including a mixer and a 3-stage low-noise amplifier (LNA). By adding a polarity-reversal switch to the receiver mixer, leakage, reflected signals, and traveling time of transmitted pulses can be measured. Another improvement is the design of the Rx's mixer and the 3-stage wide-band LNA to reduce on-chip DC blocking capacitors. Experimental results with/without reflector placed at several distances from the transceiver are performed to demonstrate the technique. Pulse traveling times are measured with 0.8 ns, 1 ns, and 1.25 ns for the distance of 10 cm, 14 cm, and 18 cm, respectively. Furthermore, reflected signals are measured separately from leakage in cases of different distances.
{"title":"A 0.18-μm CMOS fully integrated antenna pulse transceiver with leakage-cancellation technique for wide-band microwave range sensing radar","authors":"N. Khanh, K. Asada","doi":"10.1109/RFIC.2013.6569532","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569532","url":null,"abstract":"This paper presents a leakage cancellation technique for on-chip transceiver for range sensing radar. A 180-nm CMOS transceiver with on-chip antennas is implemented with a 9-11-GHz damping-pulse transmitter (Tx) and a receiver (Rx) including a mixer and a 3-stage low-noise amplifier (LNA). By adding a polarity-reversal switch to the receiver mixer, leakage, reflected signals, and traveling time of transmitted pulses can be measured. Another improvement is the design of the Rx's mixer and the 3-stage wide-band LNA to reduce on-chip DC blocking capacitors. Experimental results with/without reflector placed at several distances from the transceiver are performed to demonstrate the technique. Pulse traveling times are measured with 0.8 ns, 1 ns, and 1.25 ns for the distance of 10 cm, 14 cm, and 18 cm, respectively. Furthermore, reflected signals are measured separately from leakage in cases of different distances.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128143742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569542
C. Huang, J. Soricelli, L. Lam, M. Doherty, P. Antognetti, W. Vaillancourt
An innovative SOI SP5T switch-LNA integrated circuit is presented. The switch-LNA consists of a diplexer that provides out-of-band rejection and enables dual-band concurrent operation, a dual-band LNA with bypass attenuators, and three high linearity transmit paths. Tx paths feature 0.1 dB compression at >33 dBm input power, with >35 dB Tx to Rx isolation, and 0.8 and 1.2 dB insertion loss for low and high bands respectively. Receive paths feature 12 dB gain with 2.5-2.8 dB NF. Cascading the design with a dual-band WLAN PA, a complex dual-band front-end module can be easily constructed in a 3 x 4 mm package, which demonstrates transmit and receive LNA linearity with EVM <; 2% at >16 dBm and > - 5dBm output power respectively and compliant with the linearity requirements of the 802.11ac standard up to of 256-QAM 80 MHz operations.
本文介绍了一种创新型 SOI SP5T 开关 LNA 集成电路。该开关 LNA 由一个双工器（提供带外抑制并实现双频并发操作）、一个带旁路衰减器的双频 LNA 和三个高线性度传输路径组成。发送路径在输入功率大于 33 dBm 时具有 0.1 dB 压缩，发送到接收隔离度大于 35 dB，低频段和高频段插入损耗分别为 0.8 和 1.2 dB。接收路径具有 12 dB 增益和 2.5-2.8 dB NF。将该设计与双频 WLAN 功率放大器级联，可在 3 x 4 毫米封装内轻松构建复杂的双频前端模块，该模块的发射和接收 LNA 线性度分别为 EVM 16 dBm 和 > - 5dBm 输出功率，符合 802.11ac 标准高达 256-QAM 80 MHz 操作的线性度要求。
{"title":"Novel silicon-on-insulator SP5T switch-LNA front-end IC enabling concurrent dual-band 256-QAM 802.11ac WLAN radio operations","authors":"C. Huang, J. Soricelli, L. Lam, M. Doherty, P. Antognetti, W. Vaillancourt","doi":"10.1109/RFIC.2013.6569542","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569542","url":null,"abstract":"An innovative SOI SP5T switch-LNA integrated circuit is presented. The switch-LNA consists of a diplexer that provides out-of-band rejection and enables dual-band concurrent operation, a dual-band LNA with bypass attenuators, and three high linearity transmit paths. Tx paths feature 0.1 dB compression at >33 dBm input power, with >35 dB Tx to Rx isolation, and 0.8 and 1.2 dB insertion loss for low and high bands respectively. Receive paths feature 12 dB gain with 2.5-2.8 dB NF. Cascading the design with a dual-band WLAN PA, a complex dual-band front-end module can be easily constructed in a 3 x 4 mm package, which demonstrates transmit and receive LNA linearity with EVM <; 2% at >16 dBm and > - 5dBm output power respectively and compliant with the linearity requirements of the 802.11ac standard up to of 256-QAM 80 MHz operations.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128313356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569610
P. Candra, V. Jain, P. Cheng, J. Pekarik, R. Camillo-Castillo, P. Gray, T. Kessler, J. Gambino, J. Dunn, D. Harame
A manufacturable 130nm SiGe BiCMOS RF technology for high-performance mm-wave analog applications having a high-speed SiGe Heterojunction Bipolar Transistor (HBT) integrated into a full-featured RFCMOS is presented. The technology features a high performance (HP) SiGe HBT with fT/fMAX of 260/320 GHz, a high breakdown (HB) HBT with BVCEO of 3.5V, 130nm RF CMOS, and a full suite of passive devices. Specific device results pertaining to this BiCMOS8XP technology are discussed in this paper.
{"title":"A 130nm SiGe BiCMOS technology for mm-Wave applications featuring HBT with fT/fMAX of 260/320 GHz","authors":"P. Candra, V. Jain, P. Cheng, J. Pekarik, R. Camillo-Castillo, P. Gray, T. Kessler, J. Gambino, J. Dunn, D. Harame","doi":"10.1109/RFIC.2013.6569610","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569610","url":null,"abstract":"A manufacturable 130nm SiGe BiCMOS RF technology for high-performance mm-wave analog applications having a high-speed SiGe Heterojunction Bipolar Transistor (HBT) integrated into a full-featured RFCMOS is presented. The technology features a high performance (HP) SiGe HBT with fT/fMAX of 260/320 GHz, a high breakdown (HB) HBT with BVCEO of 3.5V, 130nm RF CMOS, and a full suite of passive devices. Specific device results pertaining to this BiCMOS8XP technology are discussed in this paper.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116521390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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