Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569599
D. Ji, Joo-Seong Jeon, Junghyun Kim
This paper proposes a new load insensitive RF power amplifier (PA) for mobile handsets using a load mismatch detection and curing technique. The PA controls a tunable output matching network (TOMN) adaptively based on the information of a mismatched load, thereby enhancing PA performances dramatically at a mismatched load without substantial performance degradation at a matched load. A load mismatch detector and TOMN can simply be implemented by using 0.18-μm silicon on insulator (SOI) FET that are integrated with 2-μm InGaP/GaAs HBT PA MMIC into a single module. To verify the idea, the PA module has been designed and implemented especially for a linearity enhancement under load mismatch condition. With WCDMA R'99 signal at 1.95 GHz, the measured results showed that ACLR at output power of 28.25 dBm was improved by as much as 13.7 dB on the worst ACLR-load angle compared to a conventional PA. In this way, the proposed load insensitive PA can keep ACLR under -37 dBc all over the load angle at 2.5:1 voltage standing wave ratio (VSWR).
{"title":"A novel load insensitive RF power amplifier using a load mismatch detection and curing technique","authors":"D. Ji, Joo-Seong Jeon, Junghyun Kim","doi":"10.1109/RFIC.2013.6569599","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569599","url":null,"abstract":"This paper proposes a new load insensitive RF power amplifier (PA) for mobile handsets using a load mismatch detection and curing technique. The PA controls a tunable output matching network (TOMN) adaptively based on the information of a mismatched load, thereby enhancing PA performances dramatically at a mismatched load without substantial performance degradation at a matched load. A load mismatch detector and TOMN can simply be implemented by using 0.18-μm silicon on insulator (SOI) FET that are integrated with 2-μm InGaP/GaAs HBT PA MMIC into a single module. To verify the idea, the PA module has been designed and implemented especially for a linearity enhancement under load mismatch condition. With WCDMA R'99 signal at 1.95 GHz, the measured results showed that ACLR at output power of 28.25 dBm was improved by as much as 13.7 dB on the worst ACLR-load angle compared to a conventional PA. In this way, the proposed load insensitive PA can keep ACLR under -37 dBc all over the load angle at 2.5:1 voltage standing wave ratio (VSWR).","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128238029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569509
A. Ebrazeh, P. Mohseni
This paper reports an all-digital impulse radio ultra wideband transmitter (IR-UWB TX) fabricated in 90-nm CMOS, which incorporates a waveform-synthesis pulse generator and a timing generator for OOK/PPM pulse modulation and scrambling. The UWB pulse generator includes ten identical taps, each comprising an impulse generator and an output driver. Upon triggering by the timing generator, these taps create a programmable number of individual lobes with 4b control over their duration and amplitude, which are then combined at a shared output node to generate the UWB pulse. With a high-performance receiver, the TX might be used for moderate-data-rate (<;50Mbps), m-range telemetry, suitable for brain-behavior studies, with energy consumption in the range of 12 to 20pJ/pulse, and for high-data-rate (>100Mbps), cm-range telemetry, suitable for brain-machine interfaces, with energy consumption in the range of 3.6 to 6pJ/pulse from 1.2V.
{"title":"An all-digital IR-UWB transmitter with a waveform-synthesis pulse generator in 90nm CMOS for high-density brain monitoring","authors":"A. Ebrazeh, P. Mohseni","doi":"10.1109/RFIC.2013.6569509","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569509","url":null,"abstract":"This paper reports an all-digital impulse radio ultra wideband transmitter (IR-UWB TX) fabricated in 90-nm CMOS, which incorporates a waveform-synthesis pulse generator and a timing generator for OOK/PPM pulse modulation and scrambling. The UWB pulse generator includes ten identical taps, each comprising an impulse generator and an output driver. Upon triggering by the timing generator, these taps create a programmable number of individual lobes with 4b control over their duration and amplitude, which are then combined at a shared output node to generate the UWB pulse. With a high-performance receiver, the TX might be used for moderate-data-rate (<;50Mbps), m-range telemetry, suitable for brain-behavior studies, with energy consumption in the range of 12 to 20pJ/pulse, and for high-data-rate (>100Mbps), cm-range telemetry, suitable for brain-machine interfaces, with energy consumption in the range of 3.6 to 6pJ/pulse from 1.2V.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569569
Shinwon Kang, A. Niknejad
A 100GHz fundamental active-varactor VCO and a bi-directionally injection-locked loop are demonstrated in 65nm CMOS. Without using a conventional passive varactor, the proposed VCO achieves a tuning range of 5.2% at 100GHz and a phase noise of -112.1dBc/Hz at 10MHz offset. By utilizing the proposed transmission-line-based capacitive coupling, four oscillators are injection-locked properly and the loop creates eight phases of the carrier and 6dB(=10log4) of phase noise improvement, realizing a measured phase noise is -118.8dBc/Hz at 10MHz offset.
{"title":"A 100GHz active-varactor VCO and a bi-directionally injection-locked loop in 65nm CMOS","authors":"Shinwon Kang, A. Niknejad","doi":"10.1109/RFIC.2013.6569569","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569569","url":null,"abstract":"A 100GHz fundamental active-varactor VCO and a bi-directionally injection-locked loop are demonstrated in 65nm CMOS. Without using a conventional passive varactor, the proposed VCO achieves a tuning range of 5.2% at 100GHz and a phase noise of -112.1dBc/Hz at 10MHz offset. By utilizing the proposed transmission-line-based capacitive coupling, four oscillators are injection-locked properly and the loop creates eight phases of the carrier and 6dB(=10log4) of phase noise improvement, realizing a measured phase noise is -118.8dBc/Hz at 10MHz offset.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132685178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569608
A. Valdes-Garcia, A. Natarajan, Duixian Liu, M. Sanduleanu, X. Gu, M. Ferriss, B. Parker, C. Baks, J. Plouchart, H. Ainspan, B. Sadhu, M. R. Islam, S. Reynolds
This paper presents a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band. 32 receive elements and 16 transmit elements with dual outputs are integrated to support 16 dual polarized antennas in a package. The IC further includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level. The fully-integrated transceiver is fabricated in the IBM SiGe BiCMOS 0.13um process, occupies an area of 6.6×6.7mm2, and operates from 2.7V (analog/RF) and 1.5V (digital) supplies. Multiple operating modes are supported including the simultaneous reception of two polarizations with a 10GHz IF output, transmission in either polarization from an IF input, or single-polarization transmission/reception from/to I&Q base-band signals (2.5W RX, 2.9W TX). Measurement results show 8dB receiver NF and 2dBm transmitter output power per element at 94GHz in both polarizations.
{"title":"A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS","authors":"A. Valdes-Garcia, A. Natarajan, Duixian Liu, M. Sanduleanu, X. Gu, M. Ferriss, B. Parker, C. Baks, J. Plouchart, H. Ainspan, B. Sadhu, M. R. Islam, S. Reynolds","doi":"10.1109/RFIC.2013.6569608","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569608","url":null,"abstract":"This paper presents a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band. 32 receive elements and 16 transmit elements with dual outputs are integrated to support 16 dual polarized antennas in a package. The IC further includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level. The fully-integrated transceiver is fabricated in the IBM SiGe BiCMOS 0.13um process, occupies an area of 6.6×6.7mm2, and operates from 2.7V (analog/RF) and 1.5V (digital) supplies. Multiple operating modes are supported including the simultaneous reception of two polarizations with a 10GHz IF output, transmission in either polarization from an IF input, or single-polarization transmission/reception from/to I&Q base-band signals (2.5W RX, 2.9W TX). Measurement results show 8dB receiver NF and 2dBm transmitter output power per element at 94GHz in both polarizations.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117257685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569545
I. Choi, Bumman Kim
This paper describes a passive mixer-first receiver front-end (RFE) for mobile TV covering 100MHz to 800MHz without any external components. The proposed input matching technique with RC discharging circuit achieves a simple topology with a low noise. The out-of-band linearity is enhanced using the low pass filtering of sampling capacitor, delivering an outstanding out-of-band linearity. The out-of-band IIP3 and IIP2 are 7dBm and 36dBm, respectively at the maximum gain setting of 36dB. The third and fifth harmonic rejection ratios (HRR) are 49dB and 42dB, respectively. The power consumption is 23mW and the maximum NF is 3.6dB. The active area occupies 0.33mm2 in 65nm CMOS technology.
{"title":"A passive mixer-first receiver front-end without external components for mobile TV applications","authors":"I. Choi, Bumman Kim","doi":"10.1109/RFIC.2013.6569545","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569545","url":null,"abstract":"This paper describes a passive mixer-first receiver front-end (RFE) for mobile TV covering 100MHz to 800MHz without any external components. The proposed input matching technique with RC discharging circuit achieves a simple topology with a low noise. The out-of-band linearity is enhanced using the low pass filtering of sampling capacitor, delivering an outstanding out-of-band linearity. The out-of-band IIP3 and IIP2 are 7dBm and 36dBm, respectively at the maximum gain setting of 36dB. The third and fifth harmonic rejection ratios (HRR) are 49dB and 42dB, respectively. The power consumption is 23mW and the maximum NF is 3.6dB. The active area occupies 0.33mm2 in 65nm CMOS technology.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121187609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569605
F. Golcuk, J. Edwards, B. Cetinoneri, Y. Atesal, Gabriel M. Rebeiz
This paper presents a 2×2 amplifier-multiplier array with on-chip antennas at 163-180 GHz in 45 nm CMOS SOI technology. The measured EIRP is > 2 dBm at 165-175 GHz with a peak value of 5 dBm at 170 GHz meeting the stringiest metal-density rules for antennas. The amplifiermultiplier architecture is scalable to N×M arrays for high EIRP and transmit power.
{"title":"A 163–180 GHz 2×2 amplifier-doubler array with peak EIRP of +5 dBm","authors":"F. Golcuk, J. Edwards, B. Cetinoneri, Y. Atesal, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2013.6569605","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569605","url":null,"abstract":"This paper presents a 2×2 amplifier-multiplier array with on-chip antennas at 163-180 GHz in 45 nm CMOS SOI technology. The measured EIRP is > 2 dBm at 165-175 GHz with a peak value of 5 dBm at 170 GHz meeting the stringiest metal-density rules for antennas. The amplifiermultiplier architecture is scalable to N×M arrays for high EIRP and transmit power.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123945706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569553
Chih-Shiang Chang, Jyh-Chyurn Guo
An ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated using 0.18μm 1.8V CMOS technology. The adoption of forward body biases (FBB) in a 3-stage distributed amplifier enables an aggressive scaling of the supply voltages and gate input voltage to 0.6V. The low voltage feature from FBB leads to more than 50% power consumption saving to 4.2mW. The measured power gain (S21) is higher than 10dB in 3.1~8.1GHz and noise figure is 2.83~4.7 dB in the wideband of 2~10GHz. Superior linearity is achieved with IIP3 as high as 4.2dBm and 12.5dBm at 6.5GHz and 10GHz, respectively.
{"title":"Ultra-low voltage and low power UWB CMOS LNA using forward body biases","authors":"Chih-Shiang Chang, Jyh-Chyurn Guo","doi":"10.1109/RFIC.2013.6569553","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569553","url":null,"abstract":"An ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated using 0.18μm 1.8V CMOS technology. The adoption of forward body biases (FBB) in a 3-stage distributed amplifier enables an aggressive scaling of the supply voltages and gate input voltage to 0.6V. The low voltage feature from FBB leads to more than 50% power consumption saving to 4.2mW. The measured power gain (S21) is higher than 10dB in 3.1~8.1GHz and noise figure is 2.83~4.7 dB in the wideband of 2~10GHz. Superior linearity is achieved with IIP3 as high as 4.2dBm and 12.5dBm at 6.5GHz and 10GHz, respectively.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121948074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569612
X. Wang, Z. Shi, J. Liu, L. Wang, R. Ma, H. Zhao, Z. Dong, C. Zhang, Albert Z. H. Wang
We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS, ultra low leakage of <;2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.
{"title":"Nano switching crossbar array ESD protection structures","authors":"X. Wang, Z. Shi, J. Liu, L. Wang, R. Ma, H. Zhao, Z. Dong, C. Zhang, Albert Z. H. Wang","doi":"10.1109/RFIC.2013.6569612","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569612","url":null,"abstract":"We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS, ultra low leakage of <;2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122120200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569588
Jose Moron Guerra, A. Siligaris, J. Lampin, F. Danneville, P. Vincent
A Fully integrated 283 GHz heterodyne receiver in 65 nm CMOS process is presented in this paper. The circuit includes a resistive differential mixer, an intermediate frequency amplifier and a 282 GHz subharmonic injection locked oscillator. The on-chip oscillator generates a 94 GHz fundamental tone but exploits a 282 GHz third harmonic. An injection signal of 47 GHz (one sixth of the RF frequency) is used to lock the oscillator on a reference. The receiver measured conversion gain is -6 dB for a DC power consumption of 97.6 mW. Simulated noise figure is 38 dB. The chip size is 820 μm × 780 μm including matching networks and DC/RF pads.
{"title":"A 283 GHz low power heterodyne receiver with on-chip local oscillator in 65 nm CMOS process","authors":"Jose Moron Guerra, A. Siligaris, J. Lampin, F. Danneville, P. Vincent","doi":"10.1109/RFIC.2013.6569588","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569588","url":null,"abstract":"A Fully integrated 283 GHz heterodyne receiver in 65 nm CMOS process is presented in this paper. The circuit includes a resistive differential mixer, an intermediate frequency amplifier and a 282 GHz subharmonic injection locked oscillator. The on-chip oscillator generates a 94 GHz fundamental tone but exploits a 282 GHz third harmonic. An injection signal of 47 GHz (one sixth of the RF frequency) is used to lock the oscillator on a reference. The receiver measured conversion gain is -6 dB for a DC power consumption of 97.6 mW. Simulated noise figure is 38 dB. The chip size is 820 μm × 780 μm including matching networks and DC/RF pads.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569565
Mohammed Abdulaziz, Anders Nejdel, Markus Törmänen, H. Sjöland
In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/√Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.
{"title":"A 3.4mW 65nm CMOS 5th order programmable active-RC channel select filter for LTE receivers","authors":"Mohammed Abdulaziz, Anders Nejdel, Markus Törmänen, H. Sjöland","doi":"10.1109/RFIC.2013.6569565","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569565","url":null,"abstract":"In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/√Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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