Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569561
Ying Chen, Y. Pei, D. Leenaerts
This paper demonstrates a dual-band LO generation system using a low phase noise single-band 40GHz VCO as the signal source. The LO generation system has two outputs: single-band LO1 at 20GHz and dual-band LO2 switchable between 10GHz and 15GHz. Implemented in 0.25-μm SiGe:C BiCMOS, the VCO achieves a phase noise of -106.8dBc/Hz at 1-MHz offset from 40GHz with a frequency tuning range of 9.7%.
{"title":"A dual-band LO generation system using a 40GHz VCO with a phase noise of −106.8dBc/Hz at 1-MHz","authors":"Ying Chen, Y. Pei, D. Leenaerts","doi":"10.1109/RFIC.2013.6569561","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569561","url":null,"abstract":"This paper demonstrates a dual-band LO generation system using a low phase noise single-band 40GHz VCO as the signal source. The LO generation system has two outputs: single-band LO1 at 20GHz and dual-band LO2 switchable between 10GHz and 15GHz. Implemented in 0.25-μm SiGe:C BiCMOS, the VCO achieves a phase noise of -106.8dBc/Hz at 1-MHz offset from 40GHz with a frequency tuning range of 9.7%.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569517
M. Babaie, A. Visweswaran, Zhuobiao He, R. Staszewski
In this paper we investigate benefits of a recently introduced clip-and-restore (C&R) oscillator for ultra-low phase noise RF applications and reconsider the original choices in light of further insight into the oscillator behavior. We also tackle undesired resonance frequencies and exploit them to facilitate clipping with proper choices of tuning capacitances. Based on the new theory, the proposed oscillator was implemented in 65-nm CMOS and verified to achieve 4 dB better phase noise and 1.8 dB better FoM than the original C&R oscillator, thus making it the lowest phase noise CMOS oscillator ever published. The measured phase noise is -145 dBc/Hz at a 3 MHz offset from a 4.2 GHz carrier. The resulting average FoM is 191 dBc/Hz and varies less than 2 dB across the tuning range. It covers the 7.28.7 GHz frequency band for a 19% tuning range, drawing 32 mA from a 1.3 V power supply.
{"title":"Ultra-low phase noise 7.2–8.7 Ghz clip-and-restore oscillator with 191 dBc/Hz FoM","authors":"M. Babaie, A. Visweswaran, Zhuobiao He, R. Staszewski","doi":"10.1109/RFIC.2013.6569517","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569517","url":null,"abstract":"In this paper we investigate benefits of a recently introduced clip-and-restore (C&R) oscillator for ultra-low phase noise RF applications and reconsider the original choices in light of further insight into the oscillator behavior. We also tackle undesired resonance frequencies and exploit them to facilitate clipping with proper choices of tuning capacitances. Based on the new theory, the proposed oscillator was implemented in 65-nm CMOS and verified to achieve 4 dB better phase noise and 1.8 dB better FoM than the original C&R oscillator, thus making it the lowest phase noise CMOS oscillator ever published. The measured phase noise is -145 dBc/Hz at a 3 MHz offset from a 4.2 GHz carrier. The resulting average FoM is 191 dBc/Hz and varies less than 2 dB across the tuning range. It covers the 7.28.7 GHz frequency band for a 19% tuning range, drawing 32 mA from a 1.3 V power supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122950032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569554
Jianxun Zhu, H. Krishnaswamy, P. Kinget
Summary form only given. A low noise amplifier is presented that uniquely achieves wide-band input matching and good low-frequency noise performance at the same time. Its topology is a hybrid of distributed amplifier and a common-source common-gate noise-canceling amplifier. The proof-of-principle prototype in 65nm CMOS operates from DC up to 9.5GHz with more than 12dB gain, achieves a minimum noise figure of 2.8dB, P1dB of -7dBm, IIP3 of +4dBm, consumes 18mW from a 1.4V power supply and occupies a total active area of 0.4mm2.
{"title":"A DC-9.5GHz noise-canceling distributed LNA in 65nm CMOS","authors":"Jianxun Zhu, H. Krishnaswamy, P. Kinget","doi":"10.1109/RFIC.2013.6569554","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569554","url":null,"abstract":"Summary form only given. A low noise amplifier is presented that uniquely achieves wide-band input matching and good low-frequency noise performance at the same time. Its topology is a hybrid of distributed amplifier and a common-source common-gate noise-canceling amplifier. The proof-of-principle prototype in 65nm CMOS operates from DC up to 9.5GHz with more than 12dB gain, achieves a minimum noise figure of 2.8dB, P1dB of -7dBm, IIP3 of +4dBm, consumes 18mW from a 1.4V power supply and occupies a total active area of 0.4mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569551
M. Alavi, G. Voicu, R. Staszewski, L. D. de Vreede, J. Long
This paper presents a 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65 nm CMOS. The proposed quadrature up-converter uses a 25% duty-cycle clock to isolate the in-phase (I) and quadrature-phase (Q) modulating signals before combining. Using a 1.2 V supply and an on-chip power combiner, the modulator provides more than 21 dBm RF output power within a frequency range of 1.36 to 2.51 GHz. The peak RF output power, overall system and drain energy efficiencies of the modulator are 22.3 dBm, 31.5%, and 39.7%, respectively. Applying digital predistortion (DPD), 64 & 256 constellation points are measured with EVM better than -30 dB. The measured noise floor is below -160 dBc/Hz, with an IQ image rejection and LO leakage of -65 and -63 dBc, respectively. Its linearity has been evaluated with WCDMA modulation. Using DPD, the linearity improves by more than 15 dB.
{"title":"A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS","authors":"M. Alavi, G. Voicu, R. Staszewski, L. D. de Vreede, J. Long","doi":"10.1109/RFIC.2013.6569551","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569551","url":null,"abstract":"This paper presents a 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65 nm CMOS. The proposed quadrature up-converter uses a 25% duty-cycle clock to isolate the in-phase (I) and quadrature-phase (Q) modulating signals before combining. Using a 1.2 V supply and an on-chip power combiner, the modulator provides more than 21 dBm RF output power within a frequency range of 1.36 to 2.51 GHz. The peak RF output power, overall system and drain energy efficiencies of the modulator are 22.3 dBm, 31.5%, and 39.7%, respectively. Applying digital predistortion (DPD), 64 & 256 constellation points are measured with EVM better than -30 dB. The measured noise floor is below -160 dBc/Hz, with an IQ image rejection and LO leakage of -65 and -63 dBc, respectively. Its linearity has been evaluated with WCDMA modulation. Using DPD, the linearity improves by more than 15 dB.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569535
Wanghua Wu, Xuefei Bai, R. Staszewski, J. Long
We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.
{"title":"A mm-Wave FMCW radar transmitter based on a multirate ADPLL","authors":"Wanghua Wu, Xuefei Bai, R. Staszewski, J. Long","doi":"10.1109/RFIC.2013.6569535","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569535","url":null,"abstract":"We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121248448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569574
A. Agah, Wei Wang, P. Asbeck, L. Larson, J. Buckwalter
A novel stacked FET digital-to-RF converter is implemented in 45-nm SOI CMOS, which shares DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high output power. The proposed architecture transmits at 1.25 Gbps for QPSK at 45GHz. This transmitter exhibits a 21.3-dBm saturated output power, while achieving a peak PAE of 16%. The circuit occupies 0.3 mm2 including pads, while the PAE and Psat remains above 13% and 18 dBm from 42 to 47 GHz.
采用45nm SOI CMOS实现了一种新型的堆叠FET数模转换器，该转换器通过I/Q数模转换器(DAC)、I/Q混频器和堆叠FET PA共享直流电流，以提供高输出功率。提出的架构在45GHz的QPSK传输速率为1.25 Gbps。该发射机的饱和输出功率为21.3 dbm，峰值PAE为16%。电路占地0.3 mm2(包括焊盘)，而PAE和Psat在42至47 GHz范围内保持在13%以上和18 dBm。
{"title":"A 42 to 47-GHz, 8-bit I/Q digital-to-RF converter with 21-dBm Psat and 16% PAE in 45-nm SOI CMOS","authors":"A. Agah, Wei Wang, P. Asbeck, L. Larson, J. Buckwalter","doi":"10.1109/RFIC.2013.6569574","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569574","url":null,"abstract":"A novel stacked FET digital-to-RF converter is implemented in 45-nm SOI CMOS, which shares DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high output power. The proposed architecture transmits at 1.25 Gbps for QPSK at 45GHz. This transmitter exhibits a 21.3-dBm saturated output power, while achieving a peak PAE of 16%. The circuit occupies 0.3 mm2 including pads, while the PAE and Psat remains above 13% and 18 dBm from 42 to 47 GHz.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127014015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569510
A. Mehra, M. Sturm, D. Hedin, R. Harjani
This paper presents a low-power noncoherent ultrawideband (UWB) impulse-radio (IR) transceiver operating at 5GHz in 0.13-μm CMOS. The super-regenerative amplifier (SRA) based energy-detection receiver utilizes early/late detection for a two-step baseband synchronization algorithm. A fully-digital transmitter generates a shaped output pulse of 1GHz 3-dB bandwidth. DLLs provide a PVTtolerant time-step resolution of 1ns over the entire symbol period and regulate the pulse generator center frequency. Measured results show a receiver efficiency of 0.32nJ/bit at 20.8Mb/s and operation with inputs as low as -70dBm. The transmitter outputs -31dBm (0.88pJ/pulse at 1Mpulse/s) with a dynamic (energy) efficiency of 16pJ/pulse.
{"title":"A 0.32nJ/bit noncoherent UWB impulse Radio transceiver with baseband synchronization and a fully digital transmitter","authors":"A. Mehra, M. Sturm, D. Hedin, R. Harjani","doi":"10.1109/RFIC.2013.6569510","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569510","url":null,"abstract":"This paper presents a low-power noncoherent ultrawideband (UWB) impulse-radio (IR) transceiver operating at 5GHz in 0.13-μm CMOS. The super-regenerative amplifier (SRA) based energy-detection receiver utilizes early/late detection for a two-step baseband synchronization algorithm. A fully-digital transmitter generates a shaped output pulse of 1GHz 3-dB bandwidth. DLLs provide a PVTtolerant time-step resolution of 1ns over the entire symbol period and regulate the pulse generator center frequency. Measured results show a receiver efficiency of 0.32nJ/bit at 20.8Mb/s and operation with inputs as low as -70dBm. The transmitter outputs -31dBm (0.88pJ/pulse at 1Mpulse/s) with a dynamic (energy) efficiency of 16pJ/pulse.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"478 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133603704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569602
Young-Pyo Hong, Kenji Mukai, H. Gheidi, S. Shinjo, P. Asbeck
In this paper, we report a DC/DC converter based on GaN HEMT's with a switching frequency of 200 MHz that can be used to generate envelope-modulated power supply voltages for use in envelope tracking power amplifiers. The converter consists of switching circuits using 0.25-um GaN HEMTs, inductor, and low pass filter, and can provide output voltages above 28V. An integrated bootstrap driver of the switching circuits is employed in order to reduce DC power consumption of the driver stage. Generation of envelope power supply voltages for 20 MHz LTE signals was demonstrated using 200 MHz switching rates with efficiency of 73%(including dissipation in final and driver stages). The chip size is 1075×990 um2.
在本文中，我们报告了一种基于GaN HEMT的DC/DC转换器，其开关频率为200 MHz，可用于产生包络调制电源电压，用于包络跟踪功率放大器。该转换器由使用0.25 um GaN hemt、电感和低通滤波器的开关电路组成，可提供28V以上的输出电压。开关电路采用集成式自举驱动，以降低驱动级的直流功耗。使用200 MHz的开关速率，以73%的效率(包括终端和驱动级的耗散)演示了20 MHz LTE信号的包络电源电压的产生。芯片尺寸为1075×990 um2。
{"title":"High efficiency GaN switching converter IC with bootstrap driver for envelope tracking applications","authors":"Young-Pyo Hong, Kenji Mukai, H. Gheidi, S. Shinjo, P. Asbeck","doi":"10.1109/RFIC.2013.6569602","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569602","url":null,"abstract":"In this paper, we report a DC/DC converter based on GaN HEMT's with a switching frequency of 200 MHz that can be used to generate envelope-modulated power supply voltages for use in envelope tracking power amplifiers. The converter consists of switching circuits using 0.25-um GaN HEMTs, inductor, and low pass filter, and can provide output voltages above 28V. An integrated bootstrap driver of the switching circuits is employed in order to reduce DC power consumption of the driver stage. Generation of envelope power supply voltages for 20 MHz LTE signals was demonstrated using 200 MHz switching rates with efficiency of 73%(including dissipation in final and driver stages). The chip size is 1075×990 um2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569530
Hao Wu, N. Wang, Yuan Du, Yen-Cheng Kuan, F. Hsiao, S. Lee, M. Tsai, C. Jou, Mau-Chung Frank Chang
A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.
{"title":"A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P1dB, out linearity for high data rate communications","authors":"Hao Wu, N. Wang, Yuan Du, Yen-Cheng Kuan, F. Hsiao, S. Lee, M. Tsai, C. Jou, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2013.6569530","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569530","url":null,"abstract":"A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"680 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133366220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569583
R. Bhat, A. Chakrabarti, H. Krishnaswamy
Switching-class PAs employing device-stacking have been recently explored to meet the challenge of efficient power amplification at mmWave frequencies at moderate power levels of around 20dBm. In this paper, we propose the use of a single-step, large-scale (8-way), 75%-efficient lumped quarterwave power combiner that is co-designed with stacked Class-Elike PA unit cells to enable a Q-band 45nm SOI CMOS PA with a peak Psat of 27.2dBm (>0.5W), peak PAE of 10.7% and 1dB flatness in Psat over nearly the entire Q-band (3346GHz). This measured output power level is approximately 5 × higher than prior reported mmWave silicon PAs. In order to support complex modulations with high average-efficiency, we also propose a novel linearizing architecture that combines largescale power combining, supply-switching for efficiency under backoff and dynamic load modulation for linearization. A second fully-integrated 42.5GHz 45nm SOI CMOS PA is implemented based on this architecture and achieves 60% of the peak efficiency at 6dB back-off.
采用器件堆叠的开关级放大器最近已经被探索，以满足在毫米波频率下在大约20dBm的中等功率水平下的有效功率放大的挑战。在本文中，我们提出使用一种单步、大规模(8路)、75%效率的集总四分之一波功率组合器，该组合器与堆叠类放大器单元共同设计，以实现q波段45nm SOI CMOS放大器，其峰值Psat为27.2dBm (>0.5W)，峰值PAE为10.7%，Psat平坦度为1dB，几乎覆盖了整个q波段(3346GHz)。该测量的输出功率水平比先前报道的毫米波硅PAs高约5倍。为了支持具有高平均效率的复杂调制，我们还提出了一种新的线性化架构，该架构结合了大规模功率组合，电源开关和动态负载调制的线性化效率。第二款完全集成的42.5GHz 45nm SOI CMOS PA基于该架构实现，在6dB回退时实现了60%的峰值效率。
{"title":"Large-scale power-combining and linearization in watt-class mmWave CMOS power amplifiers","authors":"R. Bhat, A. Chakrabarti, H. Krishnaswamy","doi":"10.1109/RFIC.2013.6569583","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569583","url":null,"abstract":"Switching-class PAs employing device-stacking have been recently explored to meet the challenge of efficient power amplification at mmWave frequencies at moderate power levels of around 20dBm. In this paper, we propose the use of a single-step, large-scale (8-way), 75%-efficient lumped quarterwave power combiner that is co-designed with stacked Class-Elike PA unit cells to enable a Q-band 45nm SOI CMOS PA with a peak Psat of 27.2dBm (>0.5W), peak PAE of 10.7% and 1dB flatness in Psat over nearly the entire Q-band (3346GHz). This measured output power level is approximately 5 × higher than prior reported mmWave silicon PAs. In order to support complex modulations with high average-efficiency, we also propose a novel linearizing architecture that combines largescale power combining, supply-switching for efficiency under backoff and dynamic load modulation for linearization. A second fully-integrated 42.5GHz 45nm SOI CMOS PA is implemented based on this architecture and achieves 60% of the peak efficiency at 6dB back-off.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131146090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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