Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569622
Monte K. Watanabe, R. Snyder, T. LaRocca
The first dynamic 4-bit, digitally-assisted GaN high power amplifier (DAPA) system transmitting 7.68Msymbol/s with 64-QAM modulation is presented. An FPGA is programmed to generate the pulse-shaped 64-QAM signal, perform envelope estimation, and time-align the RF and digital control signals arriving at the DAPA. A high-speed, level-shifting circuit converts the FPGA's low-voltage differential signaling (LVDS) DAPA control signals into single-ended logic levels required for the depletion-mode GaN HEMT DAPA auxiliary cells. Measured results show 9.6% DC power savings, 23% improved PAE, and 23% higher output power at 4% EVMRMS compared to the static PA configuration.
{"title":"Simultaneous linearity and efficiency enhancement of a digitally-assisted GaN power amplifier for 64-QAM","authors":"Monte K. Watanabe, R. Snyder, T. LaRocca","doi":"10.1109/RFIC.2013.6569622","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569622","url":null,"abstract":"The first dynamic 4-bit, digitally-assisted GaN high power amplifier (DAPA) system transmitting 7.68Msymbol/s with 64-QAM modulation is presented. An FPGA is programmed to generate the pulse-shaped 64-QAM signal, perform envelope estimation, and time-align the RF and digital control signals arriving at the DAPA. A high-speed, level-shifting circuit converts the FPGA's low-voltage differential signaling (LVDS) DAPA control signals into single-ended logic levels required for the depletion-mode GaN HEMT DAPA auxiliary cells. Measured results show 9.6% DC power savings, 23% improved PAE, and 23% higher output power at 4% EVMRMS compared to the static PA configuration.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569627
Y. Shang, Haipeng Fu, Hao Yu, Junyan Ren
One high-sensitivity CMOS superregenerative receiver is demonstrated for 96GHz mm-wave imaging based on high-Q metamaterial oscillator. Compared to traditional LC-tank based oscillator, the metamaterial oscillator is developed by folded-differential transmission-line loaded complimentary split-ring resonator (FDTLCSRR). With formed sharp stop-band, standing-wave is established with high EM-energy storage at mm-wave region for high-Q oscillatory amplification. As such, one high-sensitivity 96 GHz super-regenerative receiver is realized in 65nm CMOS with measurement results of: -78 dBm sensitivity, 0.67 fW/Hz0.5 NEP, 8.5 dB NF, 2.8mW power consumption and 0.014 mm2 core area.
{"title":"A −78dBm sensitivity super-regenerative receiver at 96 GHz with quench-controlled metamaterial oscillator in 65nm CMOS","authors":"Y. Shang, Haipeng Fu, Hao Yu, Junyan Ren","doi":"10.1109/RFIC.2013.6569627","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569627","url":null,"abstract":"One high-sensitivity CMOS superregenerative receiver is demonstrated for 96GHz mm-wave imaging based on high-Q metamaterial oscillator. Compared to traditional LC-tank based oscillator, the metamaterial oscillator is developed by folded-differential transmission-line loaded complimentary split-ring resonator (FDTLCSRR). With formed sharp stop-band, standing-wave is established with high EM-energy storage at mm-wave region for high-Q oscillatory amplification. As such, one high-sensitivity 96 GHz super-regenerative receiver is realized in 65nm CMOS with measurement results of: -78 dBm sensitivity, 0.67 fW/Hz0.5 NEP, 8.5 dB NF, 2.8mW power consumption and 0.014 mm2 core area.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122860967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569560
Qiyang Wu, S. Elabd, T. Quach, A. Mattamana, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil
An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.
{"title":"A −189 dBc/Hz FOMT wide tuning range Ka-band VCO using tunable negative capacitance and inductance redistribution","authors":"Qiyang Wu, S. Elabd, T. Quach, A. Mattamana, S. Dooley, J. Mccue, P. Orlando, G. Creech, W. Khalil","doi":"10.1109/RFIC.2013.6569560","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569560","url":null,"abstract":"An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123119752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569529
Dlovan H. Mahrof, E. Klumperink, M. S. Oude Alink, B. Nauta
Highly linear CMOS radio receivers increasingly exploit linear RF V-I conversion and passive down-mixing, followed by an OpAmp based Transimpedance Amplifier at baseband. Due to the finite OpAmp gain in wideband receivers operating with large signals, virtual ground is imperfect, inducing distortion currents. We propose to apply a negative conductance to cancel this distortion. In an RF receiver, this increases In-Band IIP3 from 9dBm to >20dBm, at the cost of 1.5dB extra NF and <;10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <;27mA up to 2GHz for 1.2V supply voltage.
{"title":"A receiver with in-band IIP3>20dBm, exploiting cancelling of OpAmp finite-gain-induced distortion via negative conductance","authors":"Dlovan H. Mahrof, E. Klumperink, M. S. Oude Alink, B. Nauta","doi":"10.1109/RFIC.2013.6569529","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569529","url":null,"abstract":"Highly linear CMOS radio receivers increasingly exploit linear RF V-I conversion and passive down-mixing, followed by an OpAmp based Transimpedance Amplifier at baseband. Due to the finite OpAmp gain in wideband receivers operating with large signals, virtual ground is imperfect, inducing distortion currents. We propose to apply a negative conductance to cancel this distortion. In an RF receiver, this increases In-Band IIP3 from 9dBm to >20dBm, at the cost of 1.5dB extra NF and <;10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <;27mA up to 2GHz for 1.2V supply voltage.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569584
N. Sarmah, B. Heinemann, U. Pfeiffer
Summary form only given. High-power, broadband power amplifiers (PA) operating in the D-band (110-170 GHz) are essential towards implementation of broadband frequency multiplier chains at sub-mmWave frequencies. In this paper we present the design of a 3-stage power amplifier (PA) with 3-dB bandwidth of 35 GHz (135-170 GHz) and implemented in 130 nm SiGe BiCMOS technology. A staggered tuning approach where the peak gain of the individual or group of individual stages are tuned at offset frequencies is used for broadband operation. In the 135-170 GHz, the small signal gain for the PA is 14-17 dB and the saturated output power (Psat) varies from 5-8 dBm and the output referred 1 dB compression point (P1dB) varies from 1-6 dBm over this frequency range. The nominal dc power consumption of this PA is 320 mW with peak PAE of 1.6%. To our best knowledge, this is the highest bandwidth reported for silicon PAs in the D band.
{"title":"A 135–170 GHz power amplifier in an advanced sige HBT technology","authors":"N. Sarmah, B. Heinemann, U. Pfeiffer","doi":"10.1109/RFIC.2013.6569584","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569584","url":null,"abstract":"Summary form only given. High-power, broadband power amplifiers (PA) operating in the D-band (110-170 GHz) are essential towards implementation of broadband frequency multiplier chains at sub-mmWave frequencies. In this paper we present the design of a 3-stage power amplifier (PA) with 3-dB bandwidth of 35 GHz (135-170 GHz) and implemented in 130 nm SiGe BiCMOS technology. A staggered tuning approach where the peak gain of the individual or group of individual stages are tuned at offset frequencies is used for broadband operation. In the 135-170 GHz, the small signal gain for the PA is 14-17 dB and the saturated output power (Psat) varies from 5-8 dBm and the output referred 1 dB compression point (P1dB) varies from 1-6 dBm over this frequency range. The nominal dc power consumption of this PA is 320 mW with peak PAE of 1.6%. To our best knowledge, this is the highest bandwidth reported for silicon PAs in the D band.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121879108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569562
Wouter Volkaerts, M. Steyaert, P. Reynaert
Summary form only given. This paper presents a new architecture for a 120GHz quadrature frequency generator with large tuning range and immunity against PA-VCO coupling. Combining the output signals of two independent oscillators, the pulling effect is removed and the oscillator can be integrated with a PA and an antenna on the same chip. This architecture also makes quadrature generation with large tuning range feasible at 120GHz. The chip is fabricated in a 45nm CMOS technology and shows a tuning range of 16.2GHz (13.5%), a phase noise of -112dBc/Hz @ 10MHz offset and a phase error of 5°.
{"title":"A 120GHz quadrature frequency generator with 16.2GHz tuning range in 45nm CMOS","authors":"Wouter Volkaerts, M. Steyaert, P. Reynaert","doi":"10.1109/RFIC.2013.6569562","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569562","url":null,"abstract":"Summary form only given. This paper presents a new architecture for a 120GHz quadrature frequency generator with large tuning range and immunity against PA-VCO coupling. Combining the output signals of two independent oscillators, the pulling effect is removed and the oscillator can be integrated with a PA and an antenna on the same chip. This architecture also makes quadrature generation with large tuning range feasible at 120GHz. The chip is fabricated in a 45nm CMOS technology and shows a tuning range of 16.2GHz (13.5%), a phase noise of -112dBc/Hz @ 10MHz offset and a phase error of 5°.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"36 8-12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131605426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569544
M. Collados, Hongli Zhang, B. Tenbroek, Hsiang-Hui Chang
To create a wide-band transmit path with high current efficiency a single-balanced passive modulator is combined with a class-B single-ended resonant driver. The linearity of such configuration is limited by a strong 3rd harmonic response of the modulator combined with a strong third-order intermodulation in the driver. A novel digital predistortion approach is presented to enable good linearity under these highly non-linear conditions. Implemented in 40nm CMOS, the modulator and driver combined consume only 45mW to deliver a +3dBm Release 99 WCDMA signal with 1.1% EVM, -54dBc ACLR and -160dBc/Hz noise in the RX band. The ACLR remains below -50dBc over temperature, frequency and TX-power without adjustment of the predistortion coefficients. The transmitter delivers +0dBm 10MHz LTE with -51dBc ACLR.
{"title":"A low-current digitally predistorted 3G-4G transmitter in 40nm CMOS","authors":"M. Collados, Hongli Zhang, B. Tenbroek, Hsiang-Hui Chang","doi":"10.1109/RFIC.2013.6569544","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569544","url":null,"abstract":"To create a wide-band transmit path with high current efficiency a single-balanced passive modulator is combined with a class-B single-ended resonant driver. The linearity of such configuration is limited by a strong 3rd harmonic response of the modulator combined with a strong third-order intermodulation in the driver. A novel digital predistortion approach is presented to enable good linearity under these highly non-linear conditions. Implemented in 40nm CMOS, the modulator and driver combined consume only 45mW to deliver a +3dBm Release 99 WCDMA signal with 1.1% EVM, -54dBc ACLR and -160dBc/Hz noise in the RX band. The ACLR remains below -50dBc over temperature, frequency and TX-power without adjustment of the predistortion coefficients. The transmitter delivers +0dBm 10MHz LTE with -51dBc ACLR.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569508
Piljae Park, Sungdo Kim, Sungchul Woo, Cheonsoo Kim
A single-chip impulse radar transceiver is presented. A high-resolution, enhanced SNR and controllability are achieved with a proposed architecture. By controlling timing between the transmit (TX) pulse and sampling clock of the receiver, echo pulses from targets are received and recovered. The TX pulse can adjust its spectrum occupancy by changing impulse shape. The 4-channel sampling receiver consists of a low noise amplifier, track and hold samplers, integrators, and a cascaded triple delay locked loop. The embedded control logic allows the radar to enhance the SNR of the received pulse using an averaging technique, and to operate at multiple reception modes. The real-time radar system measurements show that echo pulses are recovered with ≥100-psec range resolution while consuming 80 mW from 1.2-V of Vdd. An indoor human walking trace is successfully recorded. The transceiver is fabricated in a 130-nm CMOS technology occupying chip area of 3.4 mm2.
介绍了一种单片脉冲雷达收发器。该结构具有高分辨率、增强的信噪比和可控性。通过控制发射(TX)脉冲与接收机采样时钟之间的时序，接收并恢复目标的回波脉冲。TX脉冲可以通过改变脉冲形状来调节其频谱占用。4通道采样接收器由低噪声放大器、跟踪和保持采样器、积分器和级联三延迟锁定环路组成。嵌入式控制逻辑允许雷达使用平均技术提高接收脉冲的信噪比，并在多种接收模式下工作。实时雷达系统测量表明，在1.2 v Vdd消耗80 mW的情况下，回波脉冲恢复的距离分辨率≥100 psec。成功记录室内人类行走轨迹。该收发器采用130纳米CMOS技术制造，芯片面积为3.4 mm2。
{"title":"A high-resolution short-range CMOS impulse radar for human walk tracking","authors":"Piljae Park, Sungdo Kim, Sungchul Woo, Cheonsoo Kim","doi":"10.1109/RFIC.2013.6569508","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569508","url":null,"abstract":"A single-chip impulse radar transceiver is presented. A high-resolution, enhanced SNR and controllability are achieved with a proposed architecture. By controlling timing between the transmit (TX) pulse and sampling clock of the receiver, echo pulses from targets are received and recovered. The TX pulse can adjust its spectrum occupancy by changing impulse shape. The 4-channel sampling receiver consists of a low noise amplifier, track and hold samplers, integrators, and a cascaded triple delay locked loop. The embedded control logic allows the radar to enhance the SNR of the received pulse using an averaging technique, and to operate at multiple reception modes. The real-time radar system measurements show that echo pulses are recovered with ≥100-psec range resolution while consuming 80 mW from 1.2-V of Vdd. An indoor human walking trace is successfully recorded. The transceiver is fabricated in a 130-nm CMOS technology occupying chip area of 3.4 mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569625
S. Ikeda, T. Kamimura, Sang-yeop Lee, Hiroyuki Ito, N. Ishihara, K. Masu
This paper proposes an ultra-low-power 5.5GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forward-body-bias (FBB) technique, is employed for linear-frequency-tuning under the power supply of 0.5 V. The proposed PLL was fabricated in 65 nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106 dBc/Hz, a reference spur level lower than -65 dBc, and the total power consumption of 950μW at 5.5 GHz.
{"title":"A sub-1mw 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation","authors":"S. Ikeda, T. Kamimura, Sang-yeop Lee, Hiroyuki Ito, N. Ishihara, K. Masu","doi":"10.1109/RFIC.2013.6569625","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569625","url":null,"abstract":"This paper proposes an ultra-low-power 5.5GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forward-body-bias (FBB) technique, is employed for linear-frequency-tuning under the power supply of 0.5 V. The proposed PLL was fabricated in 65 nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106 dBc/Hz, a reference spur level lower than -65 dBc, and the total power consumption of 950μW at 5.5 GHz.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115651449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569582
Farid Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, S. Pamarti
A fully integrated 60GHz CMOS PA with a PSAT of 22.6dBm is presented. To our knowledge, this is the highest reported PSAT at mm-waves in standard CMOS. To achieve a high power level, 32 differential PAs are combined through a network of transmission lines, Wilkinson combiners, and a multi-port argyle transformer. This method of combining minimizes loss while implementing a low impedance load (~12Ω) at the drains of each of the last stage PAs. Electromigration and other reliability issues are discussed.
{"title":"A fully integrated 22.6dBm mm-Wave PA in 40nm CMOS","authors":"Farid Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, S. Pamarti","doi":"10.1109/RFIC.2013.6569582","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569582","url":null,"abstract":"A fully integrated 60GHz CMOS PA with a PSAT of 22.6dBm is presented. To our knowledge, this is the highest reported PSAT at mm-waves in standard CMOS. To achieve a high power level, 32 differential PAs are combined through a network of transmission lines, Wilkinson combiners, and a multi-port argyle transformer. This method of combining minimizes loss while implementing a low impedance load (~12Ω) at the drains of each of the last stage PAs. Electromigration and other reliability issues are discussed.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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