Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569539
J. Plouchart, M. Ferriss, B. Sadhu, M. Sanduleanu, B. Parker, S. Reynolds
A 73.9-83.5 GHz synthesizer is implemented in a 130nm SiGe BiCMOS technology. The measured phase noise at 10KHz and 10MHz offset of the 82.4GHz carrier are -88.5dBc/Hz and -111dBc/Hz respectively. Reference spurs are -67 dBc. The synthesizer integrates voltage regulators and power management for SoC applications; it consumes 0.51 W from 1.5 V and 2.7 V supplies, and occupies 0.85 mm × 2.9 mm.
{"title":"A 73.9–83.5GHz synthesizer with −111dBc/Hz phase noise at 10MHz offset in a 130nm SiGe BiCMOS technology","authors":"J. Plouchart, M. Ferriss, B. Sadhu, M. Sanduleanu, B. Parker, S. Reynolds","doi":"10.1109/RFIC.2013.6569539","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569539","url":null,"abstract":"A 73.9-83.5 GHz synthesizer is implemented in a 130nm SiGe BiCMOS technology. The measured phase noise at 10KHz and 10MHz offset of the 82.4GHz carrier are -88.5dBc/Hz and -111dBc/Hz respectively. Reference spurs are -67 dBc. The synthesizer integrates voltage regulators and power management for SoC applications; it consumes 0.51 W from 1.5 V and 2.7 V supplies, and occupies 0.85 mm × 2.9 mm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133996236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569618
Teng Yang, Karthik Tripurari, H. Krishnaswamy, P. Kinget
In this paper, a harmonic rejection mixer architecture capable of operating for a wide range of LO frequencies is demonstrated. The mixer can be configured to suppress any particular harmonic of the LO or multiple harmonics simultaneously. The level of suppression of each harmonic is controlled by a set of independent gain and phase tuning parameters. Feasibility of extension of this concept to higher order harmonics is also demonstrated. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. The mixer consumes 17mW of power from a 1V power supply while occupying an area of 0.352mm2.
{"title":"A 0.5GHz–1.5GHz order scalable harmonic rejection mixer","authors":"Teng Yang, Karthik Tripurari, H. Krishnaswamy, P. Kinget","doi":"10.1109/RFIC.2013.6569618","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569618","url":null,"abstract":"In this paper, a harmonic rejection mixer architecture capable of operating for a wide range of LO frequencies is demonstrated. The mixer can be configured to suppress any particular harmonic of the LO or multiple harmonics simultaneously. The level of suppression of each harmonic is controlled by a set of independent gain and phase tuning parameters. Feasibility of extension of this concept to higher order harmonics is also demonstrated. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. The mixer consumes 17mW of power from a 1V power supply while occupying an area of 0.352mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114767019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569626
Kun-Ming Chen, Bo-Yuan Chen, Hsueh-Wei Chen, C. Chiu, G. Huang, Chia-Hao Chang, Hsin-Hui Hu
In this work, we investigated the effects of drift region resistance on the temperature behaviors of RF power LDMOS transistors. Devices with various implant doses in the drift region were fabricated. Owing to the quasi-saturation effect, the transconductances at high gate voltages are less dependent on the temperature for low-drift-dose device. In addition, the maximum oscillation frequency exhibits different temperature coefficients for devices with different drift doses. We derived an expression of unilateral power gain with 4th-order frequency term, and found that the drift resistance has a large influence on the device temperature characteristics at high frequencies.
{"title":"Effect of drift region resistance on temperature characteristics of RF power LDMOS transistors","authors":"Kun-Ming Chen, Bo-Yuan Chen, Hsueh-Wei Chen, C. Chiu, G. Huang, Chia-Hao Chang, Hsin-Hui Hu","doi":"10.1109/RFIC.2013.6569626","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569626","url":null,"abstract":"In this work, we investigated the effects of drift region resistance on the temperature behaviors of RF power LDMOS transistors. Devices with various implant doses in the drift region were fabricated. Owing to the quasi-saturation effect, the transconductances at high gate voltages are less dependent on the temperature for low-drift-dose device. In addition, the maximum oscillation frequency exhibits different temperature coefficients for devices with different drift doses. We derived an expression of unilateral power gain with 4th-order frequency term, and found that the drift resistance has a large influence on the device temperature characteristics at high frequencies.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122747850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569566
G. Yahalom, J. Dawson
A new design concept is proposed for a phase modulator for outphasing transmitter architectures, utilizing the phase shifting capabilities of a resonant tank and the ability to separately control the circuit properties via its components. A prototype in 65-nm CMOS achieves 12 bits of resolution, with a fast settling time of less than five carrier cycles to within 1°. The circuit is also tested as a stand-alone transmitter showing an EVM of less than 5% for 8-PSK modulation at maximum data rate, meeting the FCC requirements for operation at the medical implant communication services (MICS) band.
{"title":"A low-Q resonant tank phase modulator for outphasing transmitters","authors":"G. Yahalom, J. Dawson","doi":"10.1109/RFIC.2013.6569566","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569566","url":null,"abstract":"A new design concept is proposed for a phase modulator for outphasing transmitter architectures, utilizing the phase shifting capabilities of a resonant tank and the ability to separately control the circuit properties via its components. A prototype in 65-nm CMOS achieves 12 bits of resolution, with a fast settling time of less than five carrier cycles to within 1°. The circuit is also tested as a stand-alone transmitter showing an EVM of less than 5% for 8-PSK modulation at maximum data rate, meeting the FCC requirements for operation at the medical implant communication services (MICS) band.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133935578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569536
Y. Chao, H. Luong
An ultra-low-power millimeter-wave injection-locked frequency divider (ILFD) based on transformer-feedback and transformer-distribution technique is proposed to operate with a very small injection signal. The proposed ILFD measures a locking range from 60.9GHz to 64.7GHz with -7dBm input power while consuming 440uW, which features the minimum power consumption among all the reported V-band frequency dividers. An interesting injection-saturation phenomenon is also identified and verified by measurement results.
{"title":"A 440-μw 60-GHz injection-locked frequency divider in 65nm CMOS","authors":"Y. Chao, H. Luong","doi":"10.1109/RFIC.2013.6569536","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569536","url":null,"abstract":"An ultra-low-power millimeter-wave injection-locked frequency divider (ILFD) based on transformer-feedback and transformer-distribution technique is proposed to operate with a very small injection signal. The proposed ILFD measures a locking range from 60.9GHz to 64.7GHz with -7dBm input power while consuming 440uW, which features the minimum power consumption among all the reported V-band frequency dividers. An interesting injection-saturation phenomenon is also identified and verified by measurement results.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129966088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569580
Wei Fei, Hao Yu, W. M. Lim, Junyan Ren
Towards wide bandwidth and high output power density for 60GHz PA design in 65nm CMOS, this paper introduces a 2D differential power combining network by metamaterial-based zero-phase-shifter. Simultaneous distributed amplification and power combining can be achieved with improved performances in both power density and bandwidth. The PA measurement results show 13.2 dB gain, 8.7% PAE, 13dBm P1dB, and 20GHz bandwidth (53 to 73GHz) within an area of 0.268mm2.
{"title":"A 53-to-73GHz power amplifier with 74.5mW/mm2 output power density by 2D differential power combining in 65nm CMOS","authors":"Wei Fei, Hao Yu, W. M. Lim, Junyan Ren","doi":"10.1109/RFIC.2013.6569580","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569580","url":null,"abstract":"Towards wide bandwidth and high output power density for 60GHz PA design in 65nm CMOS, this paper introduces a 2D differential power combining network by metamaterial-based zero-phase-shifter. Simultaneous distributed amplification and power combining can be achieved with improved performances in both power density and bandwidth. The PA measurement results show 13.2 dB gain, 8.7% PAE, 13dBm P1dB, and 20GHz bandwidth (53 to 73GHz) within an area of 0.268mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127128031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569549
M. Buck, M. Grözing, M. Berroth, M. Epp, S. Chartier
A 0.25 μm SiGe-BiCMOS 6.4 GS/s track-and-hold circuit with an input bandwidth exceeding 6 GHz and up to 2 Vpp-diff input voltage range applies a hold-mode muted preamplifier that reduces signal feedthrough and improves linearity. The track-and-hold circuit provides more than 59 dBc hold-mode SFDR3 for 1.0 to 6.0 GHz 1 Vpp-diff input signals at 6.4 GS/s, outperforming the best commercial THs operated at only 4 GS/s.
{"title":"A 6 Ghz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS","authors":"M. Buck, M. Grözing, M. Berroth, M. Epp, S. Chartier","doi":"10.1109/RFIC.2013.6569549","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569549","url":null,"abstract":"A 0.25 μm SiGe-BiCMOS 6.4 GS/s track-and-hold circuit with an input bandwidth exceeding 6 GHz and up to 2 Vpp-diff input voltage range applies a hold-mode muted preamplifier that reduces signal feedthrough and improves linearity. The track-and-hold circuit provides more than 59 dBc hold-mode SFDR3 for 1.0 to 6.0 GHz 1 Vpp-diff input signals at 6.4 GS/s, outperforming the best commercial THs operated at only 4 GS/s.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134558790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569521
Jian Yao, Zuochang Ye, Yan Wang
Summary form only given. In this paper, an automatic parameter extraction and scalable modeling method for transformer with 2π-based equivalent circuit-topology is established for the first time. In contrast to traditional optimization extraction, the adaptive boundary compression technique, combining a new correlated parameter extraction method with the neighboring geometry parameters, is introduced. The method is validated by 42 industry transformers and both accuracy and scalability have been achieved.
{"title":"An automatic parameter extraction and scalable modeling method for transformers in RF circuit","authors":"Jian Yao, Zuochang Ye, Yan Wang","doi":"10.1109/RFIC.2013.6569521","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569521","url":null,"abstract":"Summary form only given. In this paper, an automatic parameter extraction and scalable modeling method for transformer with 2π-based equivalent circuit-topology is established for the first time. In contrast to traditional optimization extraction, the adaptive boundary compression technique, combining a new correlated parameter extraction method with the neighboring geometry parameters, is introduced. The method is validated by 42 industry transformers and both accuracy and scalability have been achieved.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124993124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569550
M. Mehrjoo, J. Buckwalter
A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.
{"title":"A 10-b, 300-MS/s power DAC with 6-Vpp differential swing","authors":"M. Mehrjoo, J. Buckwalter","doi":"10.1109/RFIC.2013.6569550","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569550","url":null,"abstract":"A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122412442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569519
Tzung-yin Lee, Yuh-yue Chen
This paper presents a methodology to characterize and model BJT's mismatch behavior for RFIC design. A measurement technique based on the conventional S-parameter measurement is developed to measure the mismatch behavior at high frequencies (HFs). First, besides the typical de-embedding, the bondpad mismatch is subtracted statistically from the capacitance mismatch measurement. Second, a semi-empirical methodology using physical parameters, such as window CD and vertical doping, is developed to model the measured AC mismatch behavior for transistors of different size. Finally, a systematic procedure is proposed to extract the mismatch parameters, which can be used in the SPICE Monte-Carlo mismatch simulation. The proposed mismatch modeling methodology is validated on an industrial 0.35μm RF BiCMOS process. The proposed model fits the mismatch characteristics of the key AC parameters, such as CBE, CBC, and fT at different current densities. The model also scales well with geometry for the transistors with sizes useful for RFIC application.
{"title":"HF mismatch characterization and modeling of bipolar transistors for RFIC design","authors":"Tzung-yin Lee, Yuh-yue Chen","doi":"10.1109/RFIC.2013.6569519","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569519","url":null,"abstract":"This paper presents a methodology to characterize and model BJT's mismatch behavior for RFIC design. A measurement technique based on the conventional S-parameter measurement is developed to measure the mismatch behavior at high frequencies (HFs). First, besides the typical de-embedding, the bondpad mismatch is subtracted statistically from the capacitance mismatch measurement. Second, a semi-empirical methodology using physical parameters, such as window CD and vertical doping, is developed to model the measured AC mismatch behavior for transistors of different size. Finally, a systematic procedure is proposed to extract the mismatch parameters, which can be used in the SPICE Monte-Carlo mismatch simulation. The proposed mismatch modeling methodology is validated on an industrial 0.35μm RF BiCMOS process. The proposed model fits the mismatch characteristics of the key AC parameters, such as CBE, CBC, and fT at different current densities. The model also scales well with geometry for the transistors with sizes useful for RFIC application.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128499051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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