Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474977
M. Tanjyo, N. Hamamoto, S. Umisedo, Y. Koga, H. Une, N. Maehara, Y. Kawamura, Y. Hashino, Y. Nakashima, M. Hashimoto, T. Nagayama, H. Onoda, N. Nagai, T. Horsky, S. Hahto, D. Jacobson
The cluster ion beam implanter named CLARIS has been developed for beyond 45nm device production use, which is characterized by the high productivity, high effective low energy high current, and preciseness of incident beam angle and dose uniformity. For the USJ process application, a cluster beam co-implantation is introduced. Carbon cluster co-implantation and the boron cluster beam implantation productivity are evaluated from a COO and CoC view point and compared with the conventional high current implanter.
{"title":"Improvement of productivity by cluster ion implanter: CLARIS","authors":"M. Tanjyo, N. Hamamoto, S. Umisedo, Y. Koga, H. Une, N. Maehara, Y. Kawamura, Y. Hashino, Y. Nakashima, M. Hashimoto, T. Nagayama, H. Onoda, N. Nagai, T. Horsky, S. Hahto, D. Jacobson","doi":"10.1109/IWJT.2010.5474977","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474977","url":null,"abstract":"The cluster ion beam implanter named CLARIS has been developed for beyond 45nm device production use, which is characterized by the high productivity, high effective low energy high current, and preciseness of incident beam angle and dose uniformity. For the USJ process application, a cluster beam co-implantation is introduced. Carbon cluster co-implantation and the boron cluster beam implantation productivity are evaluated from a COO and CoC view point and compared with the conventional high current implanter.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121704645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474898
Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
{"title":"A simulation study of a novel dual-channel body-tied MOSFET","authors":"Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai","doi":"10.1109/IWJT.2010.5474898","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474898","url":null,"abstract":"In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474994
Suhei Hara, Yusuke Shigenaga, S. Matsumoto, G. Fuse, S. Sakuragi
Physical relationship among regrowth of damaged layer, dopant activation and dopant diffusion has been investigated in the formation of boron shallow junction of Si under low-temperature pre-annealing (PA) and non-melt laser annealing (LA). The degree of crystal regrowth was adjusted with pre-annealing time. It is clarified that the regrowth of amorphous Si layer up to the junction depth has an important key to realize the low leakage current and to suppress the unnecessary B diffusion after LA.
{"title":"A defect behavior in boron shallow junction formation of Si under low-temperature pre-anneal and non-melt-laser anneal","authors":"Suhei Hara, Yusuke Shigenaga, S. Matsumoto, G. Fuse, S. Sakuragi","doi":"10.1109/IWJT.2010.5474994","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474994","url":null,"abstract":"Physical relationship among regrowth of damaged layer, dopant activation and dopant diffusion has been investigated in the formation of boron shallow junction of Si under low-temperature pre-annealing (PA) and non-melt laser annealing (LA). The degree of crystal regrowth was adjusted with pre-annealing time. It is clarified that the regrowth of amorphous Si layer up to the junction depth has an important key to realize the low leakage current and to suppress the unnecessary B diffusion after LA.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133083129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474896
Kuan-Yu Lu, Jyi-Tsong Lin, Y. Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan
In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.
{"title":"Characterization of a body-tied vertical MOSFET","authors":"Kuan-Yu Lu, Jyi-Tsong Lin, Y. Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan","doi":"10.1109/IWJT.2010.5474896","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474896","url":null,"abstract":"In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134067463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474985
Y. Takada, M. Muraguchi, T. Endoh, S. Nomura, K. Shiraishi
Recently, metallic source and drain is widely discussed with LSIs scaling trend. For this technology, it is essential to fabricate low resistive Ohmic contact between electrodes and the channel materials. However, it is expected that precise Schottky barrier height control for obtaining Ohmic contact is technologically difficult. One of the main reasons is that Fermi level pinning phenomena takes place when a metal/semiconductor interface is formed. Recently, we have proposed a new Ohmic contact model in which resonant tunneling through the defect levels in a Schottky barrier is an origin of Ohmic characteristics. In this paper, we have considered our propose Ohmic contact model which is compatible with interface physics concepts, such as a charge neutrality level which can describe essential properties of metal/semiconductor interfaces. We calculate the current-voltage characteristics based on our proposed model up to the operating temperature of the integrated circuits. Our calculated results show that our proposed model can reproduce linear Ohmic I-V characteristics from room temperature to the operation temperature of the integrated circuits.
{"title":"Proposal of a new electronic structure model of Ohmic contacts for the future metallic source and drain","authors":"Y. Takada, M. Muraguchi, T. Endoh, S. Nomura, K. Shiraishi","doi":"10.1109/IWJT.2010.5474985","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474985","url":null,"abstract":"Recently, metallic source and drain is widely discussed with LSIs scaling trend. For this technology, it is essential to fabricate low resistive Ohmic contact between electrodes and the channel materials. However, it is expected that precise Schottky barrier height control for obtaining Ohmic contact is technologically difficult. One of the main reasons is that Fermi level pinning phenomena takes place when a metal/semiconductor interface is formed. Recently, we have proposed a new Ohmic contact model in which resonant tunneling through the defect levels in a Schottky barrier is an origin of Ohmic characteristics. In this paper, we have considered our propose Ohmic contact model which is compatible with interface physics concepts, such as a charge neutrality level which can describe essential properties of metal/semiconductor interfaces. We calculate the current-voltage characteristics based on our proposed model up to the operating temperature of the integrated circuits. Our calculated results show that our proposed model can reproduce linear Ohmic I-V characteristics from room temperature to the operation temperature of the integrated circuits.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116358152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474901
D. Jin, W. Zhang, B. L. Guan, L. Chen, N. Hu, Y. Xiao, R. Wang
The two-dimensional temperature profile of a multi-finger power SiGe HBT is studied with the electrothermal model, which shows that there is an uneven temperature profile over the device finger for HBT with uniform finger length. Because of the positive current-temperature feedback, the uneven temperature profile will leads to an anomalous current distribution, which eventually caused the thermal instability. To improve the uneven temperature profile and enhance the thermal stability, the HBT with non-uniform finger length is designed. Considering that designing multiple finger length values becomes trivial and time-consuming for the HBT with dozens of emitter fingers, a new thermal design methodology namely Grouping and Adjusting (GA) method is proposed to shorten design time. Taking 30-finger HBT for example, a detailed design procedure is present. The calculated results show both significant improvement on the peak temperature and the uniformity of SiGe HBT with non-uniform finger length.
{"title":"Optimum design methodology for thermally stable multi-finger power SiGe HBTs","authors":"D. Jin, W. Zhang, B. L. Guan, L. Chen, N. Hu, Y. Xiao, R. Wang","doi":"10.1109/IWJT.2010.5474901","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474901","url":null,"abstract":"The two-dimensional temperature profile of a multi-finger power SiGe HBT is studied with the electrothermal model, which shows that there is an uneven temperature profile over the device finger for HBT with uniform finger length. Because of the positive current-temperature feedback, the uneven temperature profile will leads to an anomalous current distribution, which eventually caused the thermal instability. To improve the uneven temperature profile and enhance the thermal stability, the HBT with non-uniform finger length is designed. Considering that designing multiple finger length values becomes trivial and time-consuming for the HBT with dozens of emitter fingers, a new thermal design methodology namely Grouping and Adjusting (GA) method is proposed to shorten design time. Taking 30-finger HBT for example, a detailed design procedure is present. The calculated results show both significant improvement on the peak temperature and the uniformity of SiGe HBT with non-uniform finger length.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122580286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474982
Se-Kyung Oh, Ying-Ying Zhang, H. Shin, I. Han, H. Kwon, Byoungchul Park, Sang-Uk Park, J. Bok, Ga-Won Lee, Jin-Suk Wang, H. Lee
In this article, we investigated the fabrication and characteristics of Pd germanide Schottky contacts on n-type Ge substrate. It is shown that the lowest sheet resistance and uniform Pd germanide can be obtained by a one step RTP at 400 °C for 30 sec. The proposed Pd germanide/nGe contact exhibited electron Schottky barrier height and work function of 0.565~0.577 eV and 4.695~4.702 eV, respectively. Therefore, the proposed Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.
{"title":"Study on palladium germanide on Ge-on-Si substrate for nanoscale Ge channel Schottky barrier MOSFETs","authors":"Se-Kyung Oh, Ying-Ying Zhang, H. Shin, I. Han, H. Kwon, Byoungchul Park, Sang-Uk Park, J. Bok, Ga-Won Lee, Jin-Suk Wang, H. Lee","doi":"10.1109/IWJT.2010.5474982","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474982","url":null,"abstract":"In this article, we investigated the fabrication and characteristics of Pd germanide Schottky contacts on n-type Ge substrate. It is shown that the lowest sheet resistance and uniform Pd germanide can be obtained by a one step RTP at 400 °C for 30 sec. The proposed Pd germanide/nGe contact exhibited electron Schottky barrier height and work function of 0.565~0.577 eV and 4.695~4.702 eV, respectively. Therefore, the proposed Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132455228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474908
Jing Shi, P. Ci, Fei Wang, Huayan Zhang, Lianwei Wang
3D p-n junction is a new kind of detector, also suggested as energy conversion device which can be adopted in high energy physics, clean energy power source and material test. The electrochemical etching process utilizing anodization has been described as a recommendable method to fabricate 3D structure for p-n junction. However, the thickness of sidewall between two adjacent pores in the structure is usually too thin for p-type silicon to accord with technological requirement of following diffusion. In this report, pulse current was employed to manufacture satisfactory microstructure p-type silicon with thick sidewall. The 3D p-n junction based on this novel structure is promising for application in photovoltaic energy conversion and detection.
{"title":"Improved electrochemical etching for the formation of 3D p-n junction","authors":"Jing Shi, P. Ci, Fei Wang, Huayan Zhang, Lianwei Wang","doi":"10.1109/IWJT.2010.5474908","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474908","url":null,"abstract":"3D p-n junction is a new kind of detector, also suggested as energy conversion device which can be adopted in high energy physics, clean energy power source and material test. The electrochemical etching process utilizing anodization has been described as a recommendable method to fabricate 3D structure for p-n junction. However, the thickness of sidewall between two adjacent pores in the structure is usually too thin for p-type silicon to accord with technological requirement of following diffusion. In this report, pulse current was employed to manufacture satisfactory microstructure p-type silicon with thick sidewall. The 3D p-n junction based on this novel structure is promising for application in photovoltaic energy conversion and detection.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125016435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/IWJT.2010.5474995
S. Kato, T. Onizawa, T. Aoyama, K. Ikeda, Y. Ohji
Millisecond annealing (MSA), such as flash lamp annealing (FLA) and laser spike annealing, is used for dopant activation of ultra-shallow junctions (USJ) in scaled complimentary metal-oxide-semiconductor (CMOS) devices. This is because lower sheet resistance (Rs) and less dopant diffusion are achieved with MSA and these are crucial requirements for minimizing the junction depth (Xj) in state-of-the-art CMOS [1–5]. In FLA the sample is irradiated for a few milliseconds with a Xe-lamp after pre-heating to 500°C or more. The assisted heating is done either using a resistive heater or by irradiation with a halogen lamp. With lamp heating, the assisted temperature (TA) range is from 500 to 1000°C compared with from 300 to 600°C using a resistive heater. In addition, with lamp assisted heating the temperature profile can be controlled to the second order, similar to spike rapid thermal annealing (sRTA). Thus, we can use higher TA with less dopant diffusion, and higher pre-heat temperatures enable higher peak temperatures during Xe-lamp irradiation. We also used a Flexibly-Shaped-Pulse (FSP) system to control the annealing time and temperature [6–10]. By combining FSP technology with lamp assisted heating, we expect to be able to have control over a wide-range of annealing times and temperatures. In addition, this combination may produce a synergistic effect on device performance. In this report, we examine, first, the effects of high assisted temperatures. Then, we demonstrate the excellent potential of combining FSP technology and lamp assisted heating on device performance.
{"title":"Flexibly-Shaped-Pulse flash lamp annealing with assisted temperature control (FSP-FLAplus) to realize a wide range of annealing conditions","authors":"S. Kato, T. Onizawa, T. Aoyama, K. Ikeda, Y. Ohji","doi":"10.1109/IWJT.2010.5474995","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474995","url":null,"abstract":"Millisecond annealing (MSA), such as flash lamp annealing (FLA) and laser spike annealing, is used for dopant activation of ultra-shallow junctions (USJ) in scaled complimentary metal-oxide-semiconductor (CMOS) devices. This is because lower sheet resistance (Rs) and less dopant diffusion are achieved with MSA and these are crucial requirements for minimizing the junction depth (Xj) in state-of-the-art CMOS [1–5]. In FLA the sample is irradiated for a few milliseconds with a Xe-lamp after pre-heating to 500°C or more. The assisted heating is done either using a resistive heater or by irradiation with a halogen lamp. With lamp heating, the assisted temperature (TA) range is from 500 to 1000°C compared with from 300 to 600°C using a resistive heater. In addition, with lamp assisted heating the temperature profile can be controlled to the second order, similar to spike rapid thermal annealing (sRTA). Thus, we can use higher TA with less dopant diffusion, and higher pre-heat temperatures enable higher peak temperatures during Xe-lamp irradiation. We also used a Flexibly-Shaped-Pulse (FSP) system to control the annealing time and temperature [6–10]. By combining FSP technology with lamp assisted heating, we expect to be able to have control over a wide-range of annealing times and temperatures. In addition, this combination may produce a synergistic effect on device performance. In this report, we examine, first, the effects of high assisted temperatures. Then, we demonstrate the excellent potential of combining FSP technology and lamp assisted heating on device performance.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129371448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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