Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474984
S. Migita, Y. Morita, W. Mizubayashi, H. Ota
Epitaxial NiSi2 source and drain with dopant segregation technique is applied to silicon nanowire (SNW) MOSFETs. Growth of epitaxial NiSi2 is characterized by self-limiting growth behavior and stability of (111) facets. These features realize the layout of junction edges in atomic-scale. Advantage of epitaxial NiSi2 growth technique is demonstrated by performances of SNW MOSFETs.
{"title":"Epitaxial NiSi2 source and drain technology for atomic-scale junction control in silicon nanowire MOSFETs","authors":"S. Migita, Y. Morita, W. Mizubayashi, H. Ota","doi":"10.1109/IWJT.2010.5474984","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474984","url":null,"abstract":"Epitaxial NiSi2 source and drain with dopant segregation technique is applied to silicon nanowire (SNW) MOSFETs. Growth of epitaxial NiSi2 is characterized by self-limiting growth behavior and stability of (111) facets. These features realize the layout of junction edges in atomic-scale. Advantage of epitaxial NiSi2 growth technique is demonstrated by performances of SNW MOSFETs.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115576374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1µm, the breakdown voltage more than 80V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8V~2.0V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz1/2, and the current noise of less than 0.05 pA/Hz1/2.
{"title":"Design and application of the high-voltage ultra-shallow junction PJFET","authors":"Zhikuan Wang, Zhaohuan Tang, Yong Liu, Guohua Shui, Hongqi Ou, Yonghui Yang","doi":"10.1109/IWJT.2010.5474906","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474906","url":null,"abstract":"In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1µm, the breakdown voltage more than 80V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8V~2.0V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz1/2, and the current noise of less than 0.05 pA/Hz1/2.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124656510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474988
Y. Yeo
To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide contact and the source/drain region in n- and p-FETs will be examined. Integration of these approaches in advanced device architectures will be shown.
{"title":"Advanced source/drain technologies for parasitic resistance reduction","authors":"Y. Yeo","doi":"10.1109/IWJT.2010.5474988","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474988","url":null,"abstract":"To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide contact and the source/drain region in n- and p-FETs will be examined. Integration of these approaches in advanced device architectures will be shown.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132311748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5475011
K. Tang, Linjun Wang, Jian Huang, Jijun Zhang, W. Shi, Yiben Xia
Al-doped ZnO films with different Al concentrations were prepared on freestanding diamond (FSD) substrates by radio-frequency (RF) reactive magnetron sputtering method. The effects of Al concentrations and annealing process on the structural and electrical properties of the ZnO films were studied by X-ray diffraction (XRD) and Hall effect measurement system respectively. The experimental results suggested the crystalline quality of ZnO films decreased with the increase of Al doping concentrations and a maxmum carrier concentration is obtained for the film doped with 2 wt.% Al. The high temperature annealing process is helpful to enhance the Hall mobility of the films.
{"title":"Electrical and structural properties of Al-doped ZnO films","authors":"K. Tang, Linjun Wang, Jian Huang, Jijun Zhang, W. Shi, Yiben Xia","doi":"10.1109/IWJT.2010.5475011","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5475011","url":null,"abstract":"Al-doped ZnO films with different Al concentrations were prepared on freestanding diamond (FSD) substrates by radio-frequency (RF) reactive magnetron sputtering method. The effects of Al concentrations and annealing process on the structural and electrical properties of the ZnO films were studied by X-ray diffraction (XRD) and Hall effect measurement system respectively. The experimental results suggested the crystalline quality of ZnO films decreased with the increase of Al doping concentrations and a maxmum carrier concentration is obtained for the film doped with 2 wt.% Al. The high temperature annealing process is helpful to enhance the Hall mobility of the films.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121040723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474969
K. Uejima, K. Yako, T. Yamamoto, N. Ikarashi, S. Shishiguchi, T. Hase, M. Hane
An aggressive junction design concept is proposed for further scaling of bulk planar CMOS featuring selectively epi-grown raised source/drain extensions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process and carbon co-implantation. The junction design window enlarged by introducing the RSDext enables us to elaborately control slight "intentional" diffusion through the newly developed MSA process rather than aiming complete-diffusion-less junctions. Such the "effective" ultra-shallow junctions under the RSDext realized both lower parasitic resistance and lower junction leakage by eliminating current bottleneck and implant defects while maintaining superior short-channel-effect suppression. Cluster carbon co-implanted RSDext structure, which enables high boron concentration at the silicide interface and low deep halo dosage, was also effective to reduce parasitic resistance and junction leakage. We demonstrated sub-30 nm gate length CMOSFETs with one decade reduction of junction leakage, and 10% Ion improvement for both N and PFET by adapting closely positioned silicide to the gate edge (about 5 nm).
{"title":"Aggressive design of ultra-shallow junction for near-scaling-limit bulk planar CMOS by using raised source/drain extension structure and carbon co-implantion technology","authors":"K. Uejima, K. Yako, T. Yamamoto, N. Ikarashi, S. Shishiguchi, T. Hase, M. Hane","doi":"10.1109/IWJT.2010.5474969","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474969","url":null,"abstract":"An aggressive junction design concept is proposed for further scaling of bulk planar CMOS featuring selectively epi-grown raised source/drain extensions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process and carbon co-implantation. The junction design window enlarged by introducing the RSDext enables us to elaborately control slight \"intentional\" diffusion through the newly developed MSA process rather than aiming complete-diffusion-less junctions. Such the \"effective\" ultra-shallow junctions under the RSDext realized both lower parasitic resistance and lower junction leakage by eliminating current bottleneck and implant defects while maintaining superior short-channel-effect suppression. Cluster carbon co-implanted RSDext structure, which enables high boron concentration at the silicide interface and low deep halo dosage, was also effective to reduce parasitic resistance and junction leakage. We demonstrated sub-30 nm gate length CMOSFETs with one decade reduction of junction leakage, and 10% Ion improvement for both N and PFET by adapting closely positioned silicide to the gate edge (about 5 nm).","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474914
L. Zhang, M. Saitoh, M. Koike, S. Takeno, H. Tanimoto, K. Adachi, N. Yasutake, N. Kusunoki
Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this work, we demonstrate the 1-nm-spatial resolution of SSRM on pn junction delineation by comparing with three-dimensional device simulation. A five-order dynamic range of carrier concentration is also confirmed on staircase sample. A systematic comparison between pFETs/nFETs on (110) and (100) substrates has been carried out with SSRM. The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron ion implantation. We also succeeded in a new sample-making method by fully FIB pick up, enabling site-specific SSRM characteristics for failure analysis and for further scaled devices.
{"title":"High-resolution and site-specific SSRM on S/D engineering","authors":"L. Zhang, M. Saitoh, M. Koike, S. Takeno, H. Tanimoto, K. Adachi, N. Yasutake, N. Kusunoki","doi":"10.1109/IWJT.2010.5474914","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474914","url":null,"abstract":"Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this work, we demonstrate the 1-nm-spatial resolution of SSRM on pn junction delineation by comparing with three-dimensional device simulation. A five-order dynamic range of carrier concentration is also confirmed on staircase sample. A systematic comparison between pFETs/nFETs on (110) and (100) substrates has been carried out with SSRM. The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron ion implantation. We also succeeded in a new sample-making method by fully FIB pick up, enabling site-specific SSRM characteristics for failure analysis and for further scaled devices.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127291869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474983
S. Koh, C. Ng, P. Liu, Z. Mo, Xincai Wang, Hongyu Y Zheng, Zhi-Yong Zhao, N. Variam, T. Henry, Y. Erokhin, G. Samudra, Y. Yeo
We report the first demonstration of a contact technology employing a combination of low energy Aluminum (Al) ion implantation and pulsed laser anneal (PLA) to form nickel silicide (NiSi) with low hole effective Schottky barrier height (ΦBp) on Si. First, the Al implant energy is reduced over prior work to ensure compatibility with thinner NiSi contacts. Second, the effect of PLA on silicide contact formation is investigated. Third, we show that increasing Al concentration at the silicide/Si interface while keeping the Al concentration within the silicide low is vital for reducing ΦBp. Successful implementation of the contact technology leads to ~77 % reduction in ΦBp, achieving a low ΦBp of 0.104 eV. This opens up new options to lower ΦBp with reduced thermal budget for future technology generations.
{"title":"Schottky barrier height modulation with Aluminum segregation and pulsed laser anneal: A route for contact resistance reduction","authors":"S. Koh, C. Ng, P. Liu, Z. Mo, Xincai Wang, Hongyu Y Zheng, Zhi-Yong Zhao, N. Variam, T. Henry, Y. Erokhin, G. Samudra, Y. Yeo","doi":"10.1109/IWJT.2010.5474983","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474983","url":null,"abstract":"We report the first demonstration of a contact technology employing a combination of low energy Aluminum (Al) ion implantation and pulsed laser anneal (PLA) to form nickel silicide (NiSi) with low hole effective Schottky barrier height (Φ<inf>B</inf><sup>p</sup>) on Si. First, the Al implant energy is reduced over prior work to ensure compatibility with thinner NiSi contacts. Second, the effect of PLA on silicide contact formation is investigated. Third, we show that increasing Al concentration at the silicide/Si interface while keeping the Al concentration within the silicide low is vital for reducing Φ<inf>B</inf><sup>p</sup>. Successful implementation of the contact technology leads to ~77 % reduction in Φ<inf>B</inf><sup>p</sup>, achieving a low Φ<inf>B</inf><sup>p</sup> of 0.104 eV. This opens up new options to lower Φ<inf>B</inf><sup>p</sup> with reduced thermal budget for future technology generations.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474973
P. Maleki, T. Scholtes, M. Popadic, F. Sarubbi, G. Lorito, S. Milosavljevic, W. de Boer, L. Nanver
This paper presents a new method of supplying the high doses of boron needed for creating several micron deep p+n junctions. Chemical vapor deposition (CVD), in a Si/SiGe epitaxial reactor, of nanometer-thick pure boron layers is used to fabricate 5 μm deep p+n junctions. The 10 min B deposition is combined with a 195 min drive-in at 1100°C to give a resulting sheet resistance of 3.1 Ω/sq. For as-deposited B-layers in windows through an silicon dioxide isolation to the Si substrate, reactions of the Si with oxide at the perimeter of the deposited windows will be enhanced by the presence of the B-layer during the high-temperature drive-in. Detrimental effects such as lateral contact window widening, small surface defects and/or large spikes formation, are avoided by capping the surface of the windows with either thermal oxide in a selective process or a low-pressure CVD (LPCVD) oxide during the drive-in. A good electrical quality of the oxide capping layer was achieved. The surface morphology was investigated by atomic force and scanning electron microscopy (AFM/SEM) analysis and found to depend on the overall method of fabrication.
{"title":"Deep p+ junctions formed by drive-in from pure boron depositions","authors":"P. Maleki, T. Scholtes, M. Popadic, F. Sarubbi, G. Lorito, S. Milosavljevic, W. de Boer, L. Nanver","doi":"10.1109/IWJT.2010.5474973","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474973","url":null,"abstract":"This paper presents a new method of supplying the high doses of boron needed for creating several micron deep p+n junctions. Chemical vapor deposition (CVD), in a Si/SiGe epitaxial reactor, of nanometer-thick pure boron layers is used to fabricate 5 μm deep p+n junctions. The 10 min B deposition is combined with a 195 min drive-in at 1100°C to give a resulting sheet resistance of 3.1 Ω/sq. For as-deposited B-layers in windows through an silicon dioxide isolation to the Si substrate, reactions of the Si with oxide at the perimeter of the deposited windows will be enhanced by the presence of the B-layer during the high-temperature drive-in. Detrimental effects such as lateral contact window widening, small surface defects and/or large spikes formation, are avoided by capping the surface of the windows with either thermal oxide in a selective process or a low-pressure CVD (LPCVD) oxide during the drive-in. A good electrical quality of the oxide capping layer was achieved. The surface morphology was investigated by atomic force and scanning electron microscopy (AFM/SEM) analysis and found to depend on the overall method of fabrication.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115761258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474968
J. Barnett, R. Hill, W. Loh, C. Hobbs, P. Majhi, R. Jammy
The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs, and new materials, such as high mobility substrates (Ge and/or III-V based). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under reduced thermal budget environments. While advanced dopant incorporation and activation techniques continue to be developed for Si scaling, implanting ions into III-V materials presents a fundamental problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. These challenges require the development of novel junction processing techniques that are inherently defect-free and can be controlled at the nm scale. One such promising technique, monolayer doping (MLD), is reviewed in this article.
{"title":"Advanced techniques for achieving ultra-shallow junctions in future CMOS devices","authors":"J. Barnett, R. Hill, W. Loh, C. Hobbs, P. Majhi, R. Jammy","doi":"10.1109/IWJT.2010.5474968","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474968","url":null,"abstract":"The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs, and new materials, such as high mobility substrates (Ge and/or III-V based). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under reduced thermal budget environments. While advanced dopant incorporation and activation techniques continue to be developed for Si scaling, implanting ions into III-V materials presents a fundamental problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. These challenges require the development of novel junction processing techniques that are inherently defect-free and can be controlled at the nm scale. One such promising technique, monolayer doping (MLD), is reviewed in this article.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474910
Yanying Wang, Dong Zhang, Yuqiang Lv, Dawei Gong, K. Shao, Zhongjian Wang, D. He, Xinhong Cheng
HV LDMOS on SOI has found wide applications such as lighting electronics and motor control due to its advantages over conventional LDMOS on bulk silicon. However, the design of optimized junctions with high breakdown voltages is commonly recognized to be difficult. This is partly because of the lack of analytical knowledge for the junctions design. In this study, various junctions were simulated by TCAD and analyzed from semiconductor physics point of view. It includes not only the junctions showing high breakdown voltages (>600V) but also the junctions showing relatively low breakdown voltages. The electrical field distribution, electrostatic potential distribution, depletion region and mobile carriers etc. were compared and analyzed to explain the reasons why a high breakdown voltage can be achieved for some junctions. Additionally, the breakdown voltage dependence on drift region doping profile was also studied.
{"title":"A simulation study of SOI RESURF junctions for HV LDMOS (>600V)","authors":"Yanying Wang, Dong Zhang, Yuqiang Lv, Dawei Gong, K. Shao, Zhongjian Wang, D. He, Xinhong Cheng","doi":"10.1109/IWJT.2010.5474910","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474910","url":null,"abstract":"HV LDMOS on SOI has found wide applications such as lighting electronics and motor control due to its advantages over conventional LDMOS on bulk silicon. However, the design of optimized junctions with high breakdown voltages is commonly recognized to be difficult. This is partly because of the lack of analytical knowledge for the junctions design. In this study, various junctions were simulated by TCAD and analyzed from semiconductor physics point of view. It includes not only the junctions showing high breakdown voltages (>600V) but also the junctions showing relatively low breakdown voltages. The electrical field distribution, electrostatic potential distribution, depletion region and mobile carriers etc. were compared and analyzed to explain the reasons why a high breakdown voltage can be achieved for some junctions. Additionally, the breakdown voltage dependence on drift region doping profile was also studied.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121863708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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