Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474996
S. Higashi
We have developed millisecond annealing technique using an atmospheric pressure DC arc discharge thermal plasma jet (TPJ). Noncontact monitoring of wafer surface temperature is performed on the basis of transient reflectivity of silicon wafer observed during TPJ irradiation. As and B implanted silicon wafers were annealed and the impurity activation was investigated. In the case of As+-implanted samples, efficient dopant activation was observed at a temperature higher than 1000 K, while it was observed at a temperature higher than 1400 K in the case of B-implanted samples. The sheet resistance (RS) of B-implanted samples monotonically decreases with temperature, and no significant dependence on heating rate (Rh) or cooling rate (Rc) is observed. On the other hand, As+-implanted samples show significant dependence of RS on Rh and Rc. We have performed TPJ annealing on an As2+-implanted sample, and obtained an ultrashallow junction (USJ) with a junction depth (Xj) of 11.9 nm and a RS of 1095 Ω/sq. B USJ is also obtained with a Xj of 23.5 nm and a RS of 392 Ω/sq. Precise control of Rh and Rc in addition to annealing temperature is quite important for achieving highly efficient doping in USJ.
{"title":"Millisecond annealing induced by atmospheric pressure thermal plasma jet irradiation and its application to ultra shallow junction formation","authors":"S. Higashi","doi":"10.1109/IWJT.2010.5474996","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474996","url":null,"abstract":"We have developed millisecond annealing technique using an atmospheric pressure DC arc discharge thermal plasma jet (TPJ). Noncontact monitoring of wafer surface temperature is performed on the basis of transient reflectivity of silicon wafer observed during TPJ irradiation. As and B implanted silicon wafers were annealed and the impurity activation was investigated. In the case of As<sup>+</sup>-implanted samples, efficient dopant activation was observed at a temperature higher than 1000 K, while it was observed at a temperature higher than 1400 K in the case of B-implanted samples. The sheet resistance (R<inf>S</inf>) of B-implanted samples monotonically decreases with temperature, and no significant dependence on heating rate (R<inf>h</inf>) or cooling rate (R<inf>c</inf>) is observed. On the other hand, As<sup>+</sup>-implanted samples show significant dependence of R<inf>S</inf> on R<inf>h</inf> and R<inf>c</inf>. We have performed TPJ annealing on an As<inf>2</inf><sup>+</sup>-implanted sample, and obtained an ultrashallow junction (USJ) with a junction depth (X<inf>j</inf>) of 11.9 nm and a R<inf>S</inf> of 1095 Ω/sq. B USJ is also obtained with a X<inf>j</inf> of 23.5 nm and a R<inf>S</inf> of 392 Ω/sq. Precise control of R<inf>h</inf> and R<inf>c</inf> in addition to annealing temperature is quite important for achieving highly efficient doping in USJ.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123575269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474980
S. Shibata, F. Kawase, A. Kitada, T. Kouzaki, A. Kitamura, K. Yamazawa, M. Arai, Y. Nambu, H. Izutani, T. Morita
We have applied spectroscopic ellipsometry (SE) to measure amorphized layer thickness after implantation and solid phase re-growth at low annealing temperatures as a non-destructive, in line implant monitoring technique. The SE measurement treats the heavily damaged layer as a part of the amorphized layer. And it is an area very sensitive to the temperature. Therefore, this sensitivity of detecting the heavily damaged layer can be used for monitoring the performance and conditions of individual implanters. In this paper, we examine the thickness of amorphous and heavily-damaged interface layers formed by Clusterion implantation (B10Hx, B16Hy, B36Hz, C5Ha, C7Hb, C16Hc), by helium ions in a plasma doping tool, and single ion implantation. In addition, we report on behavior in the amorphous layer formed by As ion implantation with a heat-treatment of 100–600 degree C.
{"title":"Evaluation by spectroscopic ellipsometryof Si amorphized layer thickness after implantation and solid phase re-growth at low annealing temperatures","authors":"S. Shibata, F. Kawase, A. Kitada, T. Kouzaki, A. Kitamura, K. Yamazawa, M. Arai, Y. Nambu, H. Izutani, T. Morita","doi":"10.1109/IWJT.2010.5474980","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474980","url":null,"abstract":"We have applied spectroscopic ellipsometry (SE) to measure amorphized layer thickness after implantation and solid phase re-growth at low annealing temperatures as a non-destructive, in line implant monitoring technique. The SE measurement treats the heavily damaged layer as a part of the amorphized layer. And it is an area very sensitive to the temperature. Therefore, this sensitivity of detecting the heavily damaged layer can be used for monitoring the performance and conditions of individual implanters. In this paper, we examine the thickness of amorphous and heavily-damaged interface layers formed by Clusterion implantation (B10Hx, B16Hy, B36Hz, C5Ha, C7Hb, C16Hc), by helium ions in a plasma doping tool, and single ion implantation. In addition, we report on behavior in the amorphous layer formed by As ion implantation with a heat-treatment of 100–600 degree C.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474902
Hongyu He, Xueren Zheng
Temperature effect of grain boundary barrier height is simulated considering double exponentials distribution trap states. Two threshold voltage definitions are compared, gate voltage when maximum barrier height occurs and when the condition of equal trapped and free charge interface. And grain size dependence of threshold voltage is also present and compared. Low electric field mobility is computed based on the barrier height model. The results show that barrier height is less dependent on temperature, and more dependent on the trap states density or grain size.
{"title":"Grain boundary barrier height and threshold voltage model of polycrystalline silicon thin film transistors","authors":"Hongyu He, Xueren Zheng","doi":"10.1109/IWJT.2010.5474902","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474902","url":null,"abstract":"Temperature effect of grain boundary barrier height is simulated considering double exponentials distribution trap states. Two threshold voltage definitions are compared, gate voltage when maximum barrier height occurs and when the condition of equal trapped and free charge interface. And grain size dependence of threshold voltage is also present and compared. Low electric field mobility is computed based on the barrier height model. The results show that barrier height is less dependent on temperature, and more dependent on the trap states density or grain size.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127702716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474999
H. Kiyama, S. Kato, T. Aoyama, T. Onizawa, K. Ikeda, H. Kondo, K. Hashimoto, H. Murakawa, Toru Kuroiwa
Idea of a very short time annealing technology has evaluated in 1980s. Engineers tried to use Flash lamp, laser or some other lamps [1]. In 1990s, W-halogen lamp annealing replaced furnace annealing in activation and silicidation process. Thermal budget has reduced from minutes to seconds. Eager for Milli-second Annealing (MSA) really came out in 2000s. Since dopant diffusion and an activation ratio have been considered to be more critical obstacle in scaled down microstructure devices, FLA activation technology came into spotlight again [2–9]. A 65nm device was a first product which used Flash Lamp Annealing (FLA) in manufacturing. Today, milli-second process has become an indispensable method in device manufacturing. But device generation keeps proceeding 45nm, 32nm and so on. Furthermore, a new material like high-k/metal is selected as a latest device material. Difficulty in MSA for 32 and 22 generation devices is reported recently.
{"title":"Advanced Flash Lamp Annealing technology for 22nm and further device","authors":"H. Kiyama, S. Kato, T. Aoyama, T. Onizawa, K. Ikeda, H. Kondo, K. Hashimoto, H. Murakawa, Toru Kuroiwa","doi":"10.1109/IWJT.2010.5474999","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474999","url":null,"abstract":"Idea of a very short time annealing technology has evaluated in 1980s. Engineers tried to use Flash lamp, laser or some other lamps [1]. In 1990s, W-halogen lamp annealing replaced furnace annealing in activation and silicidation process. Thermal budget has reduced from minutes to seconds. Eager for Milli-second Annealing (MSA) really came out in 2000s. Since dopant diffusion and an activation ratio have been considered to be more critical obstacle in scaled down microstructure devices, FLA activation technology came into spotlight again [2–9]. A 65nm device was a first product which used Flash Lamp Annealing (FLA) in manufacturing. Today, milli-second process has become an indispensable method in device manufacturing. But device generation keeps proceeding 45nm, 32nm and so on. Furthermore, a new material like high-k/metal is selected as a latest device material. Difficulty in MSA for 32 and 22 generation devices is reported recently.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474916
Yonggen He, Yong Chen, Guobin Yu, Albert Hong, J. Lu, Xianghua Liu, Lu Yu, Yueling Chen
Laser spike anneal (LSA) is one of major millisecond anneal techniques for forming ultra-shallow and highly activated junctions. With its ultra-fast heating capability, LSA has found a range of applications in ultra-shallow junction (USJ) applications. However, there are some challenges associated with the technique that need to be effectively addressed to ensure the quality of LSA processes. One of such challenges is macro and micro non-uniformity resulted from LSA process. In this work, the non-uniformity was studied using modulated optical reflectance (MOR) and sheet resistance measurement by four point probe. Significant macro and micro non-uniformity was observed through these metrologies. The impact of LSA process knobs, such as scanning method, overlap percentage and rotation on non-uniformity was investigated.
{"title":"Laser spike anneal macro & micro non-uniformity investigation using modulated optical reflectance and four-point-probe","authors":"Yonggen He, Yong Chen, Guobin Yu, Albert Hong, J. Lu, Xianghua Liu, Lu Yu, Yueling Chen","doi":"10.1109/IWJT.2010.5474916","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474916","url":null,"abstract":"Laser spike anneal (LSA) is one of major millisecond anneal techniques for forming ultra-shallow and highly activated junctions. With its ultra-fast heating capability, LSA has found a range of applications in ultra-shallow junction (USJ) applications. However, there are some challenges associated with the technique that need to be effectively addressed to ensure the quality of LSA processes. One of such challenges is macro and micro non-uniformity resulted from LSA process. In this work, the non-uniformity was studied using modulated optical reflectance (MOR) and sheet resistance measurement by four point probe. Significant macro and micro non-uniformity was observed through these metrologies. The impact of LSA process knobs, such as scanning method, overlap percentage and rotation on non-uniformity was investigated.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132712325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474997
J. Lu, Yonggen He, Yong Chen
As CMOS devices are scaled down, dopant activation, junction profile control and silicide engineering become increasingly important. To address these ultra-shallow junction (USJ) challenges, millisecond anneal (MSA) has emerged as a main stream thermal process technology for advanced CMOS device fabrication. In this paper, we will discuss two major classes of applications for MSA in USJ: achieving effective dopant activation with limited diffusion and to facilitate Ni-based silicidation with reduced leakage. Some issues and process solutions to address them will also be examined.
{"title":"Millisecond anneal for ultra-shallow junction applications","authors":"J. Lu, Yonggen He, Yong Chen","doi":"10.1109/IWJT.2010.5474997","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474997","url":null,"abstract":"As CMOS devices are scaled down, dopant activation, junction profile control and silicide engineering become increasingly important. To address these ultra-shallow junction (USJ) challenges, millisecond anneal (MSA) has emerged as a main stream thermal process technology for advanced CMOS device fabrication. In this paper, we will discuss two major classes of applications for MSA in USJ: achieving effective dopant activation with limited diffusion and to facilitate Ni-based silicidation with reduced leakage. Some issues and process solutions to address them will also be examined.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474971
J. Wei, C. W. Lee, L. Li
In this study, it was demonstrated that full semiconductor device yield can be achieved using SWNT solutions prepared by selective functionalization of SWNTs with diazonium reagents and followed by density gradient ultracentrifugation (DGU) to remove most of M species and impurities. By increasing the network thickness, the effective mobility of the devices can be raised to ~10 cm2/V⋅s while keeping the on-off ratio higher than 5000. According to the positive relationship between effective mobility and network thickness, it is possible to tune the mobility of solution processed SWNT transistors by controlling the thickness of SWNT films. The removal of impurities is found to be essential for achieving high on-off ratio devices. Instead, removal of M species is crucial to obtain good on-off characteristics. It is speculated that the achievement of the full semiconductor device yield using the SWNTs consisting of small diameter tubes is due to the significant differences between chiralities in terms of the reactivity with diazonium salts.
{"title":"Carbon nanotube thin film transistor devices","authors":"J. Wei, C. W. Lee, L. Li","doi":"10.1109/IWJT.2010.5474971","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474971","url":null,"abstract":"In this study, it was demonstrated that full semiconductor device yield can be achieved using SWNT solutions prepared by selective functionalization of SWNTs with diazonium reagents and followed by density gradient ultracentrifugation (DGU) to remove most of M species and impurities. By increasing the network thickness, the effective mobility of the devices can be raised to ~10 cm2/V⋅s while keeping the on-off ratio higher than 5000. According to the positive relationship between effective mobility and network thickness, it is possible to tune the mobility of solution processed SWNT transistors by controlling the thickness of SWNT films. The removal of impurities is found to be essential for achieving high on-off ratio devices. Instead, removal of M species is crucial to obtain good on-off characteristics. It is speculated that the achievement of the full semiconductor device yield using the SWNTs consisting of small diameter tubes is due to the significant differences between chiralities in terms of the reactivity with diazonium salts.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114438955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474990
Lars Knoll, Qing-Tai Zhao, S. Habicht, C. Urban, Konstantin Bourdelle, S. Mantl
Ultra thin Ni-silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained Si-on-insulator (SSOI) substrates. Epitaxial NiSi2 layers were formed with a 3 nm Ni layer at T>400°C, while a polycrystalline NiSi layer was with a 5nm thick Ni layer. The NiSi2 layer quality advances with increasing temperature. A very thin Pt interlayer, to incorporate Pt into NiSi, forming Ni1-xPtxSi, improves the thermal stability, the interface roughness and lowers the contact resistivity. The Schottky barrier heights (SBH) of these silicides were measured on n-Si(100). Ni1-xPtxSi shows the highest SBH. The SBH of NiSi2 layers decreases by improving the layer interface. Surprisingly, the contact resistivity of epitaxial NiSi2 is about one order of magnitude lower than that of NiSi on both, As and B doped SOI and SSOI, The lowest value of 7×10−8 Ω cm2 was measured on B doped SSOI.
{"title":"Formation and characterization of ultra-thin Ni silicides on strained and unstrained silicon","authors":"Lars Knoll, Qing-Tai Zhao, S. Habicht, C. Urban, Konstantin Bourdelle, S. Mantl","doi":"10.1109/IWJT.2010.5474990","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474990","url":null,"abstract":"Ultra thin Ni-silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained Si-on-insulator (SSOI) substrates. Epitaxial NiSi<inf>2</inf> layers were formed with a 3 nm Ni layer at T>400°C, while a polycrystalline NiSi layer was with a 5nm thick Ni layer. The NiSi<inf>2</inf> layer quality advances with increasing temperature. A very thin Pt interlayer, to incorporate Pt into NiSi, forming Ni<inf>1-x</inf>Pt<inf>x</inf>Si, improves the thermal stability, the interface roughness and lowers the contact resistivity. The Schottky barrier heights (SBH) of these silicides were measured on n-Si(100). Ni<inf>1-x</inf>Pt<inf>x</inf>Si shows the highest SBH. The SBH of NiSi<inf>2</inf> layers decreases by improving the layer interface. Surprisingly, the contact resistivity of epitaxial NiSi<inf>2</inf> is about one order of magnitude lower than that of NiSi on both, As and B doped SOI and SSOI, The lowest value of 7×10<sup>−8</sup> Ω cm<sup>2</sup> was measured on B doped SSOI.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5475010
Jian Huang, Linjun Wang, K. Tang, R. Xu, Jijun Zhang, Yiben Xia, Xionggang Lu
Boron-doped p-type nanocrystalline diamond (NCD) films were grown by microwave plasma chemical vapor deposition (MPCVD) method via introduction of the gas mixtures of methane, hydrogen and diborane. The effects of B/C ratios of gas mixtures on the electrical properties of NCD films were investigated by Hall effect measurement system. N-type ZnO films were prepared on NCD films by radio-frequency (RF) magnetron sputtering method. The dependence of electrical resistivity and carrier concentration of ZnO thin films on oxygen partial pressure was studied. In addition, I-V characteristic of the n-ZnO / p-NCD heterojunction was measured. The results showed a rectifying behavior of this structure.
{"title":"Heterojunction fabricated by deposition of ZnO films on boron-doped nanocrystalline diamond film","authors":"Jian Huang, Linjun Wang, K. Tang, R. Xu, Jijun Zhang, Yiben Xia, Xionggang Lu","doi":"10.1109/IWJT.2010.5475010","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5475010","url":null,"abstract":"Boron-doped p-type nanocrystalline diamond (NCD) films were grown by microwave plasma chemical vapor deposition (MPCVD) method via introduction of the gas mixtures of methane, hydrogen and diborane. The effects of B/C ratios of gas mixtures on the electrical properties of NCD films were investigated by Hall effect measurement system. N-type ZnO films were prepared on NCD films by radio-frequency (RF) magnetron sputtering method. The dependence of electrical resistivity and carrier concentration of ZnO thin films on oxygen partial pressure was studied. In addition, I-V characteristic of the n-ZnO / p-NCD heterojunction was measured. The results showed a rectifying behavior of this structure.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127424945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-10DOI: 10.1109/IWJT.2010.5474898
Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
{"title":"A simulation study of a novel dual-channel body-tied MOSFET","authors":"Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai","doi":"10.1109/IWJT.2010.5474898","DOIUrl":"https://doi.org/10.1109/IWJT.2010.5474898","url":null,"abstract":"In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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