Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569211
Byungyang Ahn
Gaussian random number generators are employed to simulate the fading phenomena and additive white Gaussian noise of the radio channel. High speed Gaussian random number generators are most important components for the real-time channel simulation of the CDMA systems, because of channel's wideband nature. In this paper we suggest a Gaussian random number generation method, based on central limit theorem with the simple probability density conversion before addition. Using this technique, we can omit some of the input random numbers and adders, which are relatively complex components in the hardware logic of the random number generator.
{"title":"A study on a high-speed Gaussian random number generator","authors":"Byungyang Ahn","doi":"10.1109/APCAS.1996.569211","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569211","url":null,"abstract":"Gaussian random number generators are employed to simulate the fading phenomena and additive white Gaussian noise of the radio channel. High speed Gaussian random number generators are most important components for the real-time channel simulation of the CDMA systems, because of channel's wideband nature. In this paper we suggest a Gaussian random number generation method, based on central limit theorem with the simple probability density conversion before addition. Using this technique, we can omit some of the input random numbers and adders, which are relatively complex components in the hardware logic of the random number generator.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81272128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569303
J. Ho, H. Cam Luong
A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.
{"title":"A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC","authors":"J. Ho, H. Cam Luong","doi":"10.1109/APCAS.1996.569303","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569303","url":null,"abstract":"A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89560852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569311
E. Kuh, J. Mao, M.L. Wang
Interconnect analysis modeling, and simulation will play a major role in the future design of submicron IC and electronic packaging. Existing simulation methods by and large depend on convolution and the well-known Pade approximation of transcendental functions which characterize transmission lines. Unfortunately, Pade approximation does not guarantee stability. In this paper two methods are presented. One is based on using the concept of passivity, and the other uses the traditional method of characteristics. Preliminary results obtained on simple examples are very encouraging.
{"title":"Interconnect simulation based on passivity and method of characteristics","authors":"E. Kuh, J. Mao, M.L. Wang","doi":"10.1109/APCAS.1996.569311","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569311","url":null,"abstract":"Interconnect analysis modeling, and simulation will play a major role in the future design of submicron IC and electronic packaging. Existing simulation methods by and large depend on convolution and the well-known Pade approximation of transcendental functions which characterize transmission lines. Unfortunately, Pade approximation does not guarantee stability. In this paper two methods are presented. One is based on using the concept of passivity, and the other uses the traditional method of characteristics. Preliminary results obtained on simple examples are very encouraging.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77684331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569279
W. Tsai, C. Shung, D.C. Wang
A power estimation tool is required to be faster and more accurate when the power consumption is the chief concern during chip design. A logic-level simulator is a good choice for estimating the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use the logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and the time interval of two consecutive transitions to decide whether these transitions are partial glitches or full transitions. We estimate the transition power of each transition event and summed them. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.
{"title":"Accurate logic-level power simulation using glitch filtering and estimation","authors":"W. Tsai, C. Shung, D.C. Wang","doi":"10.1109/APCAS.1996.569279","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569279","url":null,"abstract":"A power estimation tool is required to be faster and more accurate when the power consumption is the chief concern during chip design. A logic-level simulator is a good choice for estimating the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use the logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and the time interval of two consecutive transitions to decide whether these transitions are partial glitches or full transitions. We estimate the transition power of each transition event and summed them. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91508005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569205
K. Takaya, R. T. Reinhardt
Low bit-rate facial image coding for intended applications to video telephone is presented. The basic principle for this facial image coding is to use 2D image warping techniques in generating successive video frames from a stored master image. Setting global and local grids, the use of attractant/repellant masses, and bilinear mapping for painting a picture are described along with the necessary image analysis for parameter extraction.
{"title":"Low bit-rate image coding for facial movement","authors":"K. Takaya, R. T. Reinhardt","doi":"10.1109/APCAS.1996.569205","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569205","url":null,"abstract":"Low bit-rate facial image coding for intended applications to video telephone is presented. The basic principle for this facial image coding is to use 2D image warping techniques in generating successive video frames from a stored master image. Setting global and local grids, the use of attractant/repellant masses, and bilinear mapping for painting a picture are described along with the necessary image analysis for parameter extraction.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90320874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569268
I. Yamashita
Current strong demands on computer communication services like internet access services require economical solutions to provide broadband capabilities to access networks. Several approaches to broaden the so-called access bottleneck have been proposed and tested, that is, HFC using cable modems, metallic cables using ADSL, wireless access, FTTC using VDSL and FTTH. In this paper, the latest technologies to realize economically feasible FTTH systems are presented. The requirements and system technologies to provide various multimedia services as well as conventional telephone services are shown. Various approaches to reduce the access network cost are introduced from system and component technologies point of views. Three types of FTTH systems, Narrowband FTTH, Video Distribution FTTH and High Speed FTTH based on ATM techniques are presented. The international collaboration on full service access networks is discussed. Finally, the field trials of FTTH in Japan are illustrated.
{"title":"The latest FTTH technologies for full service access networks","authors":"I. Yamashita","doi":"10.1109/APCAS.1996.569268","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569268","url":null,"abstract":"Current strong demands on computer communication services like internet access services require economical solutions to provide broadband capabilities to access networks. Several approaches to broaden the so-called access bottleneck have been proposed and tested, that is, HFC using cable modems, metallic cables using ADSL, wireless access, FTTC using VDSL and FTTH. In this paper, the latest technologies to realize economically feasible FTTH systems are presented. The requirements and system technologies to provide various multimedia services as well as conventional telephone services are shown. Various approaches to reduce the access network cost are introduced from system and component technologies point of views. Three types of FTTH systems, Narrowband FTTH, Video Distribution FTTH and High Speed FTTH based on ATM techniques are presented. The international collaboration on full service access networks is discussed. Finally, the field trials of FTTH in Japan are illustrated.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91007215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569315
Toshinori Yamada, S. Ueno
This paper presents a practical fault-tolerant architecture for mesh parallel machines that has only one spare processor and has only six communication links per processor while tolerating one processor fault and one communication link fault, or two communication link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most six.
{"title":"Fault-tolerant meshes with efficient layouts","authors":"Toshinori Yamada, S. Ueno","doi":"10.1109/APCAS.1996.569315","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569315","url":null,"abstract":"This paper presents a practical fault-tolerant architecture for mesh parallel machines that has only one spare processor and has only six communication links per processor while tolerating one processor fault and one communication link fault, or two communication link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most six.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82594148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569269
D. Gajski
With recent success in VLSI and CAD technologies more and more companies are looking into tradeoffs for the complete product specification, design and manufacturing in order to increase their market share or time-to-market for their products. This new emphasis moves the focus of design sciences into areas of market research, requirements capture and analysis, executable specification generation, system exploration with different architectures, technologies and libraries and software/hardware/mechanical codesign where the future productivity gain is the largest. With this new emphasis companies are trying to shorten the conceptualization, design and manufacturing time in order to introduce new models every year. In this paper we propose a design methodology that can shorten the design cycle significantly. This is achieved by specifying the design at the highest level of abstractions and using powerful tools to complete the rest of the design. We also reflect on a design example that was generated using this methodology.
{"title":"Methodology is the future","authors":"D. Gajski","doi":"10.1109/APCAS.1996.569269","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569269","url":null,"abstract":"With recent success in VLSI and CAD technologies more and more companies are looking into tradeoffs for the complete product specification, design and manufacturing in order to increase their market share or time-to-market for their products. This new emphasis moves the focus of design sciences into areas of market research, requirements capture and analysis, executable specification generation, system exploration with different architectures, technologies and libraries and software/hardware/mechanical codesign where the future productivity gain is the largest. With this new emphasis companies are trying to shorten the conceptualization, design and manufacturing time in order to introduce new models every year. In this paper we propose a design methodology that can shorten the design cycle significantly. This is achieved by specifying the design at the highest level of abstractions and using powerful tools to complete the rest of the design. We also reflect on a design example that was generated using this methodology.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83576191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569272
M. Yagyu, M. Shiratori, A. Nishihara
Linear phase FIR digital filters whose coefficients are expressed as canonic signed digit (CSD) code can be efficiently realized by using a small number of adders and subtractors instead of multipliers. Common uses of the adders and subtractors can further reduce the number of adders and subtractors (NAS). The use of additional adders and subtractors to recover the reduction can improve the frequency responses of those filters. An algorithm to optimize the frequency responses of such filters is proposed. Many examples confirm that, using the specified NAS, the obtained filters leave better frequency responses compared to the conventional CSD structures.
{"title":"Design of linear phase FIR digital filters using minimal number of adders and subtractors","authors":"M. Yagyu, M. Shiratori, A. Nishihara","doi":"10.1109/APCAS.1996.569272","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569272","url":null,"abstract":"Linear phase FIR digital filters whose coefficients are expressed as canonic signed digit (CSD) code can be efficiently realized by using a small number of adders and subtractors instead of multipliers. Common uses of the adders and subtractors can further reduce the number of adders and subtractors (NAS). The use of additional adders and subtractors to recover the reduction can improve the frequency responses of those filters. An algorithm to optimize the frequency responses of such filters is proposed. Many examples confirm that, using the specified NAS, the obtained filters leave better frequency responses compared to the conventional CSD structures.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90070352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569213
C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim
This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.
{"title":"An implementation of the 155M physical layer ASIC for ATM network-node interface","authors":"C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim","doi":"10.1109/APCAS.1996.569213","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569213","url":null,"abstract":"This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74603936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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