Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569249
H. Hong, Sung-Hyun Han, G. Hong, Jongsoo Choi
This paper presents an efficient simulation method that generates thermal images and gives tracking results of infra-red (IR) reticle seekers. We first construct an IR model of the target having an internal heat source, and generate thermal images produced by the optical system of the reticle seeker and atmospheric turbulence. Using the generated thermal images, we can simulate IR seekers in various cases including countermeasures such as flares. Simulation results show that our method generates accurate images and the constructed loop is applicable to the study of the development of counter-countermeasures.
{"title":"Simulation of reticle seekers using the generated thermal images","authors":"H. Hong, Sung-Hyun Han, G. Hong, Jongsoo Choi","doi":"10.1109/APCAS.1996.569249","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569249","url":null,"abstract":"This paper presents an efficient simulation method that generates thermal images and gives tracking results of infra-red (IR) reticle seekers. We first construct an IR model of the target having an internal heat source, and generate thermal images produced by the optical system of the reticle seeker and atmospheric turbulence. Using the generated thermal images, we can simulate IR seekers in various cases including countermeasures such as flares. Simulation results show that our method generates accurate images and the constructed loop is applicable to the study of the development of counter-countermeasures.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"4 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88472033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569305
Haksoo Han, Hyunsoo Chung, Sungkook Park, Y. Joe, Sungsoon Park, Gwanchong Joo, N. Hwang, H. Lee, Kang Seungoo, Song Min-Kyu
The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead (Pb: 350/spl deg/C) and the Indium (In: 157/spl deg/C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5/spl sim/6 /spl mu/m thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30 /spl mu/m was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10/spl sim/40 /spl mu/m according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230/spl plusmn/5/spl deg/C.
{"title":"Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices","authors":"Haksoo Han, Hyunsoo Chung, Sungkook Park, Y. Joe, Sungsoon Park, Gwanchong Joo, N. Hwang, H. Lee, Kang Seungoo, Song Min-Kyu","doi":"10.1109/APCAS.1996.569305","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569305","url":null,"abstract":"The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead (Pb: 350/spl deg/C) and the Indium (In: 157/spl deg/C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5/spl sim/6 /spl mu/m thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30 /spl mu/m was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10/spl sim/40 /spl mu/m according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230/spl plusmn/5/spl deg/C.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88636974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569323
S. Lee, M. Hariyama, M. Kameyama
A high-performance VLSI architecture for 3-D instrumentation has been proposed based on a new concurrent memory access scheme. The key concept of this architecture is to reduce the number of pixel values to be retrieved and the time required in retrieving pixel values. Accordingly, the time required for the calculation of the mean-absolute difference (MAD) function is reduced and operations that involve memory access are calculated in parallel by a 2-D PE array in the MAD calculation unit (MADU).
{"title":"High-performance VLSI architecture for three-dimensional instrumentation based on a new concurrent memory-access scheme","authors":"S. Lee, M. Hariyama, M. Kameyama","doi":"10.1109/APCAS.1996.569323","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569323","url":null,"abstract":"A high-performance VLSI architecture for 3-D instrumentation has been proposed based on a new concurrent memory access scheme. The key concept of this architecture is to reduce the number of pixel values to be retrieved and the time required in retrieving pixel values. Accordingly, the time required for the calculation of the mean-absolute difference (MAD) function is reduced and operations that involve memory access are calculated in parallel by a 2-D PE array in the MAD calculation unit (MADU).","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"96 1","pages":"500-503"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88068318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569237
Yeong-An Jeong, Dong-Wook Kim, Sung-Hyun Han, Jongsoo Choi
This paper presents a new method which generates the uncovered region memory using motion estimation and shows the application of this algorithm for very low bit rate video coding in order to solve the problems of uncovered background region due to the region-based backward motion estimation. The proposed algorithm can be briefly described as this; it detects the changed region by using the information of FD (frame difference) and segmentation, and then as for only this region the backward motion estimation without transmission of shape information is carried out. Therefore, from only motion information the uncovered region background region memory is generated and updated. The contents stored in the uncovered background region memory are referred to whenever the uncovered region comes into existence. The regions with large prediction error are transformed and coded by using DCT. As a result of simulation, the proposed algorithm shows a superior improvement in the subjective and objective image quality as well as a remarkable reduction of transmission error bits.
{"title":"Application of uncovered region prediction for very low bit rate video coding","authors":"Yeong-An Jeong, Dong-Wook Kim, Sung-Hyun Han, Jongsoo Choi","doi":"10.1109/APCAS.1996.569237","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569237","url":null,"abstract":"This paper presents a new method which generates the uncovered region memory using motion estimation and shows the application of this algorithm for very low bit rate video coding in order to solve the problems of uncovered background region due to the region-based backward motion estimation. The proposed algorithm can be briefly described as this; it detects the changed region by using the information of FD (frame difference) and segmentation, and then as for only this region the backward motion estimation without transmission of shape information is carried out. Therefore, from only motion information the uncovered region background region memory is generated and updated. The contents stored in the uncovered background region memory are referred to whenever the uncovered region comes into existence. The regions with large prediction error are transformed and coded by using DCT. As a result of simulation, the proposed algorithm shows a superior improvement in the subjective and objective image quality as well as a remarkable reduction of transmission error bits.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"28 6","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91493649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569288
T. Matsumoto
Reachability problem is one of big issues in Petri net theory and it is reduced to that of free choice nets. However, a useful criterion has not been obtained for them. In this paper, some useful discussions on reachability of live free choice nets are presented; a net reduction method for a given net to the net with siphon/trap and a concept of immature siphon/trap are shown to judge the reachability of a given net.
{"title":"Reachability criterion of live free choice Petri nets","authors":"T. Matsumoto","doi":"10.1109/APCAS.1996.569288","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569288","url":null,"abstract":"Reachability problem is one of big issues in Petri net theory and it is reduced to that of free choice nets. However, a useful criterion has not been obtained for them. In this paper, some useful discussions on reachability of live free choice nets are presented; a net reduction method for a given net to the net with siphon/trap and a concept of immature siphon/trap are shown to judge the reachability of a given net.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"350-353"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91536284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569306
K. Takigawa, A. Hamada, K. Kawasaki, H. Ariyoshi
To analyze an electric power system with a lumped constant circuit model, it is necessary to simulate, in detail, the system conditions such as the states of connections of the generators. The analysis thus requires enormous time and labor. The authors noticed that the propagation characteristics of power disturbance in load cut off tests on generators of a power system are similar to the propagation characteristics of power disturbance in distributed constant circuits, and have been examining methods for simulating a power system with a distributed constant circuit. We applied the active sink method to the distributed constant circuit model of a power system to examine stabilization of power disturbance by controlling the power flow of a DC system parallel-connected to an AC system.
{"title":"Analysis of stability control of a power system with a distributed constant circuit model","authors":"K. Takigawa, A. Hamada, K. Kawasaki, H. Ariyoshi","doi":"10.1109/APCAS.1996.569306","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569306","url":null,"abstract":"To analyze an electric power system with a lumped constant circuit model, it is necessary to simulate, in detail, the system conditions such as the states of connections of the generators. The analysis thus requires enormous time and labor. The authors noticed that the propagation characteristics of power disturbance in load cut off tests on generators of a power system are similar to the propagation characteristics of power disturbance in distributed constant circuits, and have been examining methods for simulating a power system with a distributed constant circuit. We applied the active sink method to the distributed constant circuit model of a power system to examine stabilization of power disturbance by controlling the power flow of a DC system parallel-connected to an AC system.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"33 1","pages":"425-428"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82346634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569218
A. Barua
A high pole selectivity (Q/sub p/) bandpass filter realizable in MOSFET-C topology is suggested. The op-amps are used in fully balanced topology which has good power supply noise rejection. The proposed filter has low op-amp count in addition to a wide dynamic range. The circuit has been compared with conventional enhanced pole selectivity bandpass filter. The circuit is simulated by SPICE and a dynamic range of 123.39 dB is obtained for Q/sub p/ value of 60.
{"title":"Novel enhanced pole selectivity bandpass filter with large dynamic range","authors":"A. Barua","doi":"10.1109/APCAS.1996.569218","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569218","url":null,"abstract":"A high pole selectivity (Q/sub p/) bandpass filter realizable in MOSFET-C topology is suggested. The op-amps are used in fully balanced topology which has good power supply noise rejection. The proposed filter has low op-amp count in addition to a wide dynamic range. The circuit has been compared with conventional enhanced pole selectivity bandpass filter. The circuit is simulated by SPICE and a dynamic range of 123.39 dB is obtained for Q/sub p/ value of 60.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"10 1","pages":"57-60"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84359540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569257
S. Yamasaki
This study presents a signal restoration method in a block-coded still image and video, to cope with a block-loss problem at a decoder arising from an imperfect transmission through a communication channel. The feature of the proposal is that it applies a two-dimensional error correction coding technique not to the bit stream error correction, but to the signal restoration at the image plane.
{"title":"A reconstruction method of damaged two-dimensional signal blocks using error correction coding based on DFT","authors":"S. Yamasaki","doi":"10.1109/APCAS.1996.569257","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569257","url":null,"abstract":"This study presents a signal restoration method in a block-coded still image and video, to cope with a block-loss problem at a decoder arising from an imperfect transmission through a communication channel. The feature of the proposal is that it applies a two-dimensional error correction coding technique not to the bit stream error correction, but to the signal restoration at the image plane.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"14 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84631256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569297
T. Watanabe, T. Fujii
Recently, multichip modules (MCM) promise to be widely applied due to the advantage of multichip packaging. But, the routing problem for MCM is more difficult than those for VLSI or PCB because of the high packing density and high performance in MCM design. The problem is formulated as a general-area multilayer routing problem, and several algorithms have been proposed. Among these algorithms, a router of four-via routing proposed by Khoo and Cong (see IEEE Trans. CAD, vol.14, no.10, p.1277-90, 1995), named V4R, is the most efficient. V4R routes each net using no more than four interconnection vias, and it can make a better routing result than other MCM routers. However, there are some unresolved issues; for example, nets are routed in order of their terminal positions, so that more routing layers may be required even for short-length nets, or some routing layers are more congested because as many nets as possible are routed on the routing layers under consideration. In this paper, we present a hierarchical routing approach combined with V4R, aiming to improve the above-mentioned issues but also to preserve the characteristics of four-via routing and efficiency of V4R. In our proposed method, first, a routing area is divided into subareas hierarchically and then V4R is repeatedly applied in each subarea in the bottom-up way. Experimental results show that our approach is fairly good in the total routing-length compared with V4R itself.
{"title":"A hierarchical MCM routing using four-via routing","authors":"T. Watanabe, T. Fujii","doi":"10.1109/APCAS.1996.569297","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569297","url":null,"abstract":"Recently, multichip modules (MCM) promise to be widely applied due to the advantage of multichip packaging. But, the routing problem for MCM is more difficult than those for VLSI or PCB because of the high packing density and high performance in MCM design. The problem is formulated as a general-area multilayer routing problem, and several algorithms have been proposed. Among these algorithms, a router of four-via routing proposed by Khoo and Cong (see IEEE Trans. CAD, vol.14, no.10, p.1277-90, 1995), named V4R, is the most efficient. V4R routes each net using no more than four interconnection vias, and it can make a better routing result than other MCM routers. However, there are some unresolved issues; for example, nets are routed in order of their terminal positions, so that more routing layers may be required even for short-length nets, or some routing layers are more congested because as many nets as possible are routed on the routing layers under consideration. In this paper, we present a hierarchical routing approach combined with V4R, aiming to improve the above-mentioned issues but also to preserve the characteristics of four-via routing and efficiency of V4R. In our proposed method, first, a routing area is divided into subareas hierarchically and then V4R is repeatedly applied in each subarea in the bottom-up way. Experimental results show that our approach is fairly good in the total routing-length compared with V4R itself.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"2015 1","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83403912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569248
Taekyoung Kwon, Sungsoo Park, Yanghee Choi, H. Kim, S. Kwon
HEART is a software architecture to support distributed multimedia multiuser applications in high-speed networks. The proposed HEART software architecture consists of three layers, MMCP (Multimedia Multiuser Communication form) layer, the CASE (Common Application Service Elements) layer and the target application layer. The MMCP provides structured and dynamically-configured communication services to the individual applications of the CASE layer, which provides various types of basic application service elements. These can be flexibly configured and integrated for the development of target applications. The proposed HEART architecture will help to develop various distributed multimedia multiuser applications.
{"title":"HEART: a software architecture for distributed multimedia multiuser applications","authors":"Taekyoung Kwon, Sungsoo Park, Yanghee Choi, H. Kim, S. Kwon","doi":"10.1109/APCAS.1996.569248","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569248","url":null,"abstract":"HEART is a software architecture to support distributed multimedia multiuser applications in high-speed networks. The proposed HEART software architecture consists of three layers, MMCP (Multimedia Multiuser Communication form) layer, the CASE (Common Application Service Elements) layer and the target application layer. The MMCP provides structured and dynamically-configured communication services to the individual applications of the CASE layer, which provides various types of basic application service elements. These can be flexibly configured and integrated for the development of target applications. The proposed HEART architecture will help to develop various distributed multimedia multiuser applications.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"2016 1","pages":"179-182"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86488045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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