Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569259
Young-Ho Lee, M. Kawamata, T. Higuchi
This paper presents a new design method for multiplierless 2-D state-space digital filters (SSDFs). In order to eliminate multipliers in the hardware implementation, the resulting multiplierless 2-D SSDFs are designed under the constraint that all coefficients are represented by the sum of two powers-of-two terms. Thus they are attractive for low cost implementation and high-speed operation, since the signal in the filters can be processed by fewer shifting operations and additions instead of multiplications. Because of having very low roundoff noise, they can also perform highly accurate 2-D digital filtering. Here a combinatorial optimization procedure called genetic algorithm has been used to determine the coefficients. The effectiveness of the proposed method is demonstrated with a design example.
{"title":"GA-based design of multiplierless 2-D digital filters with very low roundoff noise","authors":"Young-Ho Lee, M. Kawamata, T. Higuchi","doi":"10.1109/APCAS.1996.569259","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569259","url":null,"abstract":"This paper presents a new design method for multiplierless 2-D state-space digital filters (SSDFs). In order to eliminate multipliers in the hardware implementation, the resulting multiplierless 2-D SSDFs are designed under the constraint that all coefficients are represented by the sum of two powers-of-two terms. Thus they are attractive for low cost implementation and high-speed operation, since the signal in the filters can be processed by fewer shifting operations and additions instead of multiplications. Because of having very low roundoff noise, they can also perform highly accurate 2-D digital filtering. Here a combinatorial optimization procedure called genetic algorithm has been used to determine the coefficients. The effectiveness of the proposed method is demonstrated with a design example.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88346150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569274
N. Togawa, M. Sato, T. Ohtsuki
This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: (0) detection of critical paths; (1) bipartitioning of a set of primary inputs and outputs; and (2) bipartitioning of a set of logic-blocks. In (0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In (1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In (2), the algorithm not only decreases the number of crossings between chips but also assigns the logic blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with the maximum number of required I/O blocks per chip small compared with conventional algorithms.
{"title":"A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems","authors":"N. Togawa, M. Sato, T. Ohtsuki","doi":"10.1109/APCAS.1996.569274","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569274","url":null,"abstract":"This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: (0) detection of critical paths; (1) bipartitioning of a set of primary inputs and outputs; and (2) bipartitioning of a set of logic-blocks. In (0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In (1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In (2), the algorithm not only decreases the number of crossings between chips but also assigns the logic blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with the maximum number of required I/O blocks per chip small compared with conventional algorithms.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86584626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569221
H. Mizutani
Recently, a lot of time has been required to analyze large VLSI transistor circuits and a faster algorithm was necessary. This paper describes a new system which obtains all solutions of a nonlinear circuit described by a piecewise linear function. It is expected that all solutions can be obtained in a practical time using the new method. In this paper, nonlinear circuits including Bipolar Junction Transistor (BJT) circuits are discussed, however, this method may be applied to any kind of nonlinear circuit described by a piecewise-linear function.
{"title":"An effective method to find all solutions of piecewise-linear circuits by analyzing piecewise-linear equations step by step","authors":"H. Mizutani","doi":"10.1109/APCAS.1996.569221","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569221","url":null,"abstract":"Recently, a lot of time has been required to analyze large VLSI transistor circuits and a faster algorithm was necessary. This paper describes a new system which obtains all solutions of a nonlinear circuit described by a piecewise linear function. It is expected that all solutions can be obtained in a practical time using the new method. In this paper, nonlinear circuits including Bipolar Junction Transistor (BJT) circuits are discussed, however, this method may be applied to any kind of nonlinear circuit described by a piecewise-linear function.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86629641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569293
Y. Miyanaga, K. Motoyoshi, K. Tochinai
This report introduces a new approach on a recognition system of three dimensional, i.e. 3D, objects. The proposed system is based on a restricted multi-layered neural network. For the performance evaluation of this network, the experiment in which some similar objects are used for recognition is demonstrated.
{"title":"Performance evaluation on 3-D object recognition using a restricted neural network","authors":"Y. Miyanaga, K. Motoyoshi, K. Tochinai","doi":"10.1109/APCAS.1996.569293","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569293","url":null,"abstract":"This report introduces a new approach on a recognition system of three dimensional, i.e. 3D, objects. The proposed system is based on a restricted multi-layered neural network. For the performance evaluation of this network, the experiment in which some similar objects are used for recognition is demonstrated.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82194861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569271
Uipil Chong, Soon-Jong Kim
The block processing algorithm is suitable for high speed implementation of digital filters on parallel processing systems. Roundoff noise is guided via the internal structure of the block filter using a state variable formulation. In this paper, we calculate and compare output roundoff noise gain for various block filter structures, which have not been investigated yet.
{"title":"The roundoff noise analysis for block digital filters realized in cascade form","authors":"Uipil Chong, Soon-Jong Kim","doi":"10.1109/APCAS.1996.569271","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569271","url":null,"abstract":"The block processing algorithm is suitable for high speed implementation of digital filters on parallel processing systems. Roundoff noise is guided via the internal structure of the block filter using a state variable formulation. In this paper, we calculate and compare output roundoff noise gain for various block filter structures, which have not been investigated yet.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73185740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569322
T. Cummins, J. Purcell
This paper describes the integration of ASIC and Mixed Signal design and simulation techniques in the design of a Mixed-Signal Digital Video Encoder chip which produces an analog output video signal. The result was fast time to market together with studio quality analog video output performance-66 dB typ SNR, 0.4% Differential Gain and 0.2/spl deg/ Differential Phase. A fully-automated design flow was used for the entire logic functionality of the chip in order to meet time-to-market requirements. Low die cost (compatible with hand-craft techniques) was achieved by aggressive use of CAD tools, process technology, and filter design techniques. Full functionality on first silicon was achieved by use of standard cell DACs, pads, Amplifier, and Band-Gap reference, and the use of a simulation test-bench which allowed frames of video to be simulated by the chip model, and the resultant simulation output to be captured and viewed on a video monitor. Some of the practical aspects of timing analysis and dynamic power estimation are also described.
{"title":"Design techniques for a PAL/NTSC mixed-signal video encoder with 66 dB SNR and 0.4% differential gain","authors":"T. Cummins, J. Purcell","doi":"10.1109/APCAS.1996.569322","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569322","url":null,"abstract":"This paper describes the integration of ASIC and Mixed Signal design and simulation techniques in the design of a Mixed-Signal Digital Video Encoder chip which produces an analog output video signal. The result was fast time to market together with studio quality analog video output performance-66 dB typ SNR, 0.4% Differential Gain and 0.2/spl deg/ Differential Phase. A fully-automated design flow was used for the entire logic functionality of the chip in order to meet time-to-market requirements. Low die cost (compatible with hand-craft techniques) was achieved by aggressive use of CAD tools, process technology, and filter design techniques. Full functionality on first silicon was achieved by use of standard cell DACs, pads, Amplifier, and Band-Gap reference, and the use of a simulation test-bench which allowed frames of video to be simulated by the chip model, and the resultant simulation output to be captured and viewed on a video monitor. Some of the practical aspects of timing analysis and dynamic power estimation are also described.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77521575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569233
K. Mak, H. Luong
A low-voltage MOS analog mixer using a cross-coupled pair as the core is described. The mixing operation is based on the square-law characteristic of the MOS transistor in the saturation region. Both theory and simulation show that the mixing characteristic is superior and not sensitive to device mismatches. The proposed mixer has a -3 dB frequency of 135 MHz and consumes 2 mW power. The nonlinearities of the mixer are less than 0.33% and 0.43%, and the THD is about 0.32% and 0.51%, with 0% and 5% device mismatch, respectively.
{"title":"A MOS analog mixer using a cross-coupled pair with source followers","authors":"K. Mak, H. Luong","doi":"10.1109/APCAS.1996.569233","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569233","url":null,"abstract":"A low-voltage MOS analog mixer using a cross-coupled pair as the core is described. The mixing operation is based on the square-law characteristic of the MOS transistor in the saturation region. Both theory and simulation show that the mixing characteristic is superior and not sensitive to device mismatches. The proposed mixer has a -3 dB frequency of 135 MHz and consumes 2 mW power. The nonlinearities of the mixer are less than 0.33% and 0.43%, and the THD is about 0.32% and 0.51%, with 0% and 5% device mismatch, respectively.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81042749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569331
Jeongho Shin, J. Paik, M. Kang
Recently, multichannel image restoration gains population in many applications such as color imaging systems, image sequences, etc. In the present paper, we classify many multichannel restoration techniques as Wiener and CLS approaches, which are respectively based on stochastic and deterministic models of the original image. We also compare two approaches in the sense of both restoration performance and implementational efficiency.
{"title":"Comparison between Wiener and CLS image restoration techniques for multichannel images","authors":"Jeongho Shin, J. Paik, M. Kang","doi":"10.1109/APCAS.1996.569331","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569331","url":null,"abstract":"Recently, multichannel image restoration gains population in many applications such as color imaging systems, image sequences, etc. In the present paper, we classify many multichannel restoration techniques as Wiener and CLS approaches, which are respectively based on stochastic and deterministic models of the original image. We also compare two approaches in the sense of both restoration performance and implementational efficiency.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86524752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569254
Y. Hahm
The existing coders used in the fading channels are designed under the assumption that the ideal interleaver, which removes the fading correlation of the channel, is used. With the non-ideal interleaver of finite size, however, the performance of the coded modulation system degrades rapidly when the fading is very slow. So author propose a scheme to get interleaving effects by switching base station antennas in a forward link, without additional software or hardware in small handset. We derive the theoretical upper bound on the pairwise error probability and do computer simulations for BER performance. The results show significant performance improvement in the slow fading and at least no deterioration in the fast fading over the existing systems.
{"title":"Trellis-coded 16-QAM with base station antenna switching in slow Rayleigh fading channel","authors":"Y. Hahm","doi":"10.1109/APCAS.1996.569254","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569254","url":null,"abstract":"The existing coders used in the fading channels are designed under the assumption that the ideal interleaver, which removes the fading correlation of the channel, is used. With the non-ideal interleaver of finite size, however, the performance of the coded modulation system degrades rapidly when the fading is very slow. So author propose a scheme to get interleaving effects by switching base station antennas in a forward link, without additional software or hardware in small handset. We derive the theoretical upper bound on the pairwise error probability and do computer simulations for BER performance. The results show significant performance improvement in the slow fading and at least no deterioration in the fast fading over the existing systems.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86607275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569320
K. Hirose, H. Yasuura
We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.
{"title":"A comparison of parallel multipliers with neuron MOS and CMOS technologies","authors":"K. Hirose, H. Yasuura","doi":"10.1109/APCAS.1996.569320","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569320","url":null,"abstract":"We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84847467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：