Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512241
B. Gustavsen
Passivity must be enforced on rational macromodels in order to ensure a stable time domain simulation. This paper investigates procedures for enforcing passivity for transmission line models based on the method of characteristics. Adding a conductive correction term externally to the line terminals is shown to be a robust and simple procedure for ensuring a passive model. The perturbation of the line model behavior is reduced by shaping the correction term using a low order rational function.
{"title":"Robust passivity enforcement of frequency dependent transmission line models","authors":"B. Gustavsen","doi":"10.1109/SPI.2007.4512241","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512241","url":null,"abstract":"Passivity must be enforced on rational macromodels in order to ensure a stable time domain simulation. This paper investigates procedures for enforcing passivity for transmission line models based on the method of characteristics. Adding a conductive correction term externally to the line terminals is shown to be a robust and simple procedure for ensuring a passive model. The perturbation of the line model behavior is reduced by shaping the correction term using a low order rational function.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126839103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512245
A. Ligocka, W. Bandurski
The paper is concerned with the simulation of signal propagation on low-loss highly inductive interconnect. The analytical solution of the output voltage signal is derived by solving the transmission line model of interconnect with multiple scales perturbation method of differential equation solving. The usefulness and limitations of the method are considered and some practical examples are presented.
{"title":"The low-loss interconnects simulation by perturbation methods","authors":"A. Ligocka, W. Bandurski","doi":"10.1109/SPI.2007.4512245","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512245","url":null,"abstract":"The paper is concerned with the simulation of signal propagation on low-loss highly inductive interconnect. The analytical solution of the output voltage signal is derived by solving the transmission line model of interconnect with multiple scales perturbation method of differential equation solving. The usefulness and limitations of the method are considered and some practical examples are presented.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512248
H. Osaka, Y. Uematsu, K. Yamamoto, H. Kanai, N. Chujo
We measured the differential insertion loss and the deterministic jitter for three types of differential transmission lines on a motherboard in a serial backplane bus at 2 Gbps in order to prioritize the design specifications for transmission lines. We tested three line widths having different common impedances of the lines while keeping the differential impedance at about 100 Omega, moreover varied the open stub lengths of the signal via holes. In the microstrip line, the loss and the jitter slightly depended on the line width; however, in the stripline, the loss depended on the line width and the deterministic jitter decreased almost linearly as the loss of the stripline decreased even when the impedance of the lines or the open stub length of the via holes was mismatched on the backplane. Therefore, loss design of a differential stripline pair on a motherboard is more important than impedance design in the low jitter.
{"title":"Differential insertion loss and deterministic jitter for different types of differential transmission lines in high-speed serial backplane bus","authors":"H. Osaka, Y. Uematsu, K. Yamamoto, H. Kanai, N. Chujo","doi":"10.1109/SPI.2007.4512248","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512248","url":null,"abstract":"We measured the differential insertion loss and the deterministic jitter for three types of differential transmission lines on a motherboard in a serial backplane bus at 2 Gbps in order to prioritize the design specifications for transmission lines. We tested three line widths having different common impedances of the lines while keeping the differential impedance at about 100 Omega, moreover varied the open stub lengths of the signal via holes. In the microstrip line, the loss and the jitter slightly depended on the line width; however, in the stripline, the loss depended on the line width and the deterministic jitter decreased almost linearly as the loss of the stripline decreased even when the impedance of the lines or the open stub length of the via holes was mismatched on the backplane. Therefore, loss design of a differential stripline pair on a motherboard is more important than impedance design in the low jitter.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512258
S. Pytel, G. Barnes, D. Hua, A. Moonshiram, G. Brist, R. Mellitz, S. Hall, P. Huray
As computer speeds continue to scale with Moore's law, improved transmission line modeling techniques are required for data rates greater than 3-5 gigabits per second (Gb/s). These transmission line models must accurately predict the interconnect characteristics to provide silicon designers correct channel parameters to ensure viable products. This work describes an analytic dielectric modeling methodology that produces accurate dielectric characteristics up to 40 GHz. Validation of multiple dielectric materials was performed up to 40 GHz by direct and indirect measurement techniques. The dielectric materials chosen for this study were based upon commonly available dielectrics that are suitable for high volume manufacturing in the printed wiring board industry.
{"title":"Dielectric modeling, characterization, and validation up to 40 GHz","authors":"S. Pytel, G. Barnes, D. Hua, A. Moonshiram, G. Brist, R. Mellitz, S. Hall, P. Huray","doi":"10.1109/SPI.2007.4512258","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512258","url":null,"abstract":"As computer speeds continue to scale with Moore's law, improved transmission line modeling techniques are required for data rates greater than 3-5 gigabits per second (Gb/s). These transmission line models must accurately predict the interconnect characteristics to provide silicon designers correct channel parameters to ensure viable products. This work describes an analytic dielectric modeling methodology that produces accurate dielectric characteristics up to 40 GHz. Validation of multiple dielectric materials was performed up to 40 GHz by direct and indirect measurement techniques. The dielectric materials chosen for this study were based upon commonly available dielectrics that are suitable for high volume manufacturing in the printed wiring board industry.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"633 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132592067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512262
C. Raghunandan, K. S. Sainarayanan, M. Srinivas
Process variations can have a significant impact on both device and interconnect performance in deep submicron (DSM) technologies. In this paper, authors discuss the impact of process parameter variations on bus-encoding schemes for delay minimization. It is shown that if process variability is taken into consideration, there will be a change in effective capacitance (Ceff) of the bus lines because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines (three bit bus model) of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variability on the effective capacitance of bus lines. Finally, the impact of process variations on bus-encoding schemes for delay minimization is discussed in detail.
{"title":"Impact of process variations on bus-encoding schemes for delay minimization in VLSI interconnects","authors":"C. Raghunandan, K. S. Sainarayanan, M. Srinivas","doi":"10.1109/SPI.2007.4512262","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512262","url":null,"abstract":"Process variations can have a significant impact on both device and interconnect performance in deep submicron (DSM) technologies. In this paper, authors discuss the impact of process parameter variations on bus-encoding schemes for delay minimization. It is shown that if process variability is taken into consideration, there will be a change in effective capacitance (Ceff) of the bus lines because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines (three bit bus model) of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variability on the effective capacitance of bus lines. Finally, the impact of process variations on bus-encoding schemes for delay minimization is discussed in detail.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512192
T. Rahal-Arabi, A. Muhtaroğlu, G. Taylor
In this presentation we overview the multi-discipline low power platform architecture and where improvements were made, we will show examples of low power innovations in process technology, microprocessor design, IO signaling and IO power delivery subsystems. We will show these innovations and techniques resulted in energy efficient mobile computing to the end user. We will end the presentation with industry trends and future challenges for low power designs.
{"title":"Designing for energy efficient mobile platforms","authors":"T. Rahal-Arabi, A. Muhtaroğlu, G. Taylor","doi":"10.1109/SPI.2007.4512192","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512192","url":null,"abstract":"In this presentation we overview the multi-discipline low power platform architecture and where improvements were made, we will show examples of low power innovations in process technology, microprocessor design, IO signaling and IO power delivery subsystems. We will show these innovations and techniques resulted in energy efficient mobile computing to the end user. We will end the presentation with industry trends and future challenges for low power designs.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117264489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512216
M. Telescu, P. Bréhonnet, N. Tanguy, P. Vilbé
In previous papers we presented MOR (model order reduction) methods based on the construction of a Gram matrix subsequent to a decomposition in Laguerre series. In this paper we propose an alternative solution using Kautz series, more adequate for modeling poorly damped systems.
{"title":"Stable model order reduction method using Kautz functions: Application to VLSI circuits","authors":"M. Telescu, P. Bréhonnet, N. Tanguy, P. Vilbé","doi":"10.1109/SPI.2007.4512216","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512216","url":null,"abstract":"In previous papers we presented MOR (model order reduction) methods based on the construction of a Gram matrix subsequent to a decomposition in Laguerre series. In this paper we propose an alternative solution using Kautz series, more adequate for modeling poorly damped systems.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121735553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512244
Zhaoqing Chen
Practical methods of making use of measured twinax cable S-parameters for transient circuit simulations are discussed and compared. Due to extremely long delay of the cable, most available tools fail or give inaccurate simulation results if we use the measured S-Parameters directly. Careful verification is absolutely necessary for any tool. For complex tasks like the worst-case eye diagram with nonlinear I/O devices, we still need more accurate and faster methodologies. This long delay case has been accepted as a very good benchmark for testing S-parameter based SPICE modeling tools and the transient simulation tools implemented with the S-parameter convolution method.
{"title":"Application of measured twinax cable S-parameters for transient circuit simulations","authors":"Zhaoqing Chen","doi":"10.1109/SPI.2007.4512244","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512244","url":null,"abstract":"Practical methods of making use of measured twinax cable S-parameters for transient circuit simulations are discussed and compared. Due to extremely long delay of the cable, most available tools fail or give inaccurate simulation results if we use the measured S-Parameters directly. Careful verification is absolutely necessary for any tool. For complex tasks like the worst-case eye diagram with nonlinear I/O devices, we still need more accurate and faster methodologies. This long delay case has been accepted as a very good benchmark for testing S-parameter based SPICE modeling tools and the transient simulation tools implemented with the S-parameter convolution method.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512212
N. Nakhla, M. Nakhla, R. Achar
The large number of ports in an interconnect structure is a critical limiting factor when applying model order reduction. This is due to the fact that the size of the reduced model grows rapidly with increasing the number of ports, leading to large and dense circuit matrices. To address this problem, a new method for model order reduction based on transverse partitioning and waveform relaxation is proposed, which effectively replaces the massively coupled multiport reduced model with decoupled 2 port subcircuits. In addition to preserving the advantages of model order reduction, the computational complexity of the new method grows only linearly with the number of lines.
{"title":"Model order reduction of large multiport interconnect structures using waveform relaxation techniques","authors":"N. Nakhla, M. Nakhla, R. Achar","doi":"10.1109/SPI.2007.4512212","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512212","url":null,"abstract":"The large number of ports in an interconnect structure is a critical limiting factor when applying model order reduction. This is due to the fact that the size of the reduced model grows rapidly with increasing the number of ports, leading to large and dense circuit matrices. To address this problem, a new method for model order reduction based on transverse partitioning and waveform relaxation is proposed, which effectively replaces the massively coupled multiport reduced model with decoupled 2 port subcircuits. In addition to preserving the advantages of model order reduction, the computational complexity of the new method grows only linearly with the number of lines.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512235
K. Butt, I. Jeffrey, M. Al-Qedra, Feng Ling, V. Okhmatovski
In this paper we discuss a computational framework which allows for accuracy controlled capacitance extraction in the entire package model consisting of 2.9 million elements on the conductor boundaries. The capacity for simulation of large- scale interconnects is attained through parallel implementation of a tree-based hierarchical computational algorithm. The acceleration of dense matrix-vector product resulting from the locally corrected Nystrom (LCN) discretization of the governing integral equation is effected by means of the Barnes-Hut (BH) method. The kernel-independence of the latter provides for inclusion of the dielectric substrate into the computational model without increasing the model's size by means of creation of the pertinent Green's function databases for the substrate process.
{"title":"Accurate capacitance extraction in the entire package model using a parallel kernel independent hierarchical extractor","authors":"K. Butt, I. Jeffrey, M. Al-Qedra, Feng Ling, V. Okhmatovski","doi":"10.1109/SPI.2007.4512235","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512235","url":null,"abstract":"In this paper we discuss a computational framework which allows for accuracy controlled capacitance extraction in the entire package model consisting of 2.9 million elements on the conductor boundaries. The capacity for simulation of large- scale interconnects is attained through parallel implementation of a tree-based hierarchical computational algorithm. The acceleration of dense matrix-vector product resulting from the locally corrected Nystrom (LCN) discretization of the governing integral equation is effected by means of the Barnes-Hut (BH) method. The kernel-independence of the latter provides for inclusion of the dielectric substrate into the computational model without increasing the model's size by means of creation of the pertinent Green's function databases for the substrate process.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133381484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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