Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512230
R. Dangel, C. Berger, R. Beyeler, L. Dellmann, F. Horst, T. Lamprecht, N. Meier, B. Offrein
In the long-distance telecom, local-area, and rack-to-rack link classes, optical interconnects have gradually replaced electrical interconnects. We believe that this trend will be continued in the short-distance card-backplane-card datacom link class. Convincing arguments for the predicted transition from electrical to optical interconnects are bandwidth-length advantages, density benefits, crosstalk reduction, and finally cost considerations. Based on this forecast, we currently develop a board-level optical interconnect technology facing several challenges, such as I) the manufacturing of reliable polymer waveguides, II) the elaboration of simple light-coupling concepts, III) the development of high-speed electro-optical modules, and IV) the application of cost-efficient packaging approaches. The successful mastering of all these tasks is a prerequisite for convincing high-speed system designers and porting optical interconnect technology into future product development plans. In this paper, we will present different achievements of our optical interconnect technology, e.g.: - 10 Gb/s per channel over 1 m link length, - optical link propagation loss below 0.05 dB/cm at 850 nm, - linear link densities up to 16 channels/mm, - feasibility of 2D channel arrays (e.g. 4 times 12), - a fully passive, low-cost alignment concept with a position accuracy of les 5 mum, enabling coupling losses < 0.5 dB, and - electro-optical transmitter and receiver modules operating at 10 Gb/s per channel. Finally, we will report on the successful realization of a 12 times 10 Gb/s card-to-card optical link demonstrator.
{"title":"Prospects of a polymer-waveguide-based board-level optical interconnect technology","authors":"R. Dangel, C. Berger, R. Beyeler, L. Dellmann, F. Horst, T. Lamprecht, N. Meier, B. Offrein","doi":"10.1109/SPI.2007.4512230","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512230","url":null,"abstract":"In the long-distance telecom, local-area, and rack-to-rack link classes, optical interconnects have gradually replaced electrical interconnects. We believe that this trend will be continued in the short-distance card-backplane-card datacom link class. Convincing arguments for the predicted transition from electrical to optical interconnects are bandwidth-length advantages, density benefits, crosstalk reduction, and finally cost considerations. Based on this forecast, we currently develop a board-level optical interconnect technology facing several challenges, such as I) the manufacturing of reliable polymer waveguides, II) the elaboration of simple light-coupling concepts, III) the development of high-speed electro-optical modules, and IV) the application of cost-efficient packaging approaches. The successful mastering of all these tasks is a prerequisite for convincing high-speed system designers and porting optical interconnect technology into future product development plans. In this paper, we will present different achievements of our optical interconnect technology, e.g.: - 10 Gb/s per channel over 1 m link length, - optical link propagation loss below 0.05 dB/cm at 850 nm, - linear link densities up to 16 channels/mm, - feasibility of 2D channel arrays (e.g. 4 times 12), - a fully passive, low-cost alignment concept with a position accuracy of les 5 mum, enabling coupling losses < 0.5 dB, and - electro-optical transmitter and receiver modules operating at 10 Gb/s per channel. Finally, we will report on the successful realization of a 12 times 10 Gb/s card-to-card optical link demonstrator.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116276086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512202
J. Leinhos, U. Arz
We investigate the effect of uncertainties in the cross- sectional parameters of ungrounded coplanar waveguides (CPWs) on the characteristic impedance and the propagation constant. For our calculations, a quasi-TEM model is used that takes into consideration the effects of non-ideal conductors, substrate loss and finite metallization thickness. The propagation of uncertainties is studied with the aid of Monte Carlo (MC) simulations. The effect of different manufacturing technologies is exemplified by two typical microwave substrates (AF45 and AI2O3). Furthermore, the impact of the uncertainties in the input quantities is investigated in such a way that conclusions for the design of CPWs as well as for the requirements on the accuracy of material measurement methods can be drawn.
{"title":"Effect of uncertainties in the cross-sectional parameters on the wideband electrical properties of coplanar waveguides","authors":"J. Leinhos, U. Arz","doi":"10.1109/SPI.2007.4512202","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512202","url":null,"abstract":"We investigate the effect of uncertainties in the cross- sectional parameters of ungrounded coplanar waveguides (CPWs) on the characteristic impedance and the propagation constant. For our calculations, a quasi-TEM model is used that takes into consideration the effects of non-ideal conductors, substrate loss and finite metallization thickness. The propagation of uncertainties is studied with the aid of Monte Carlo (MC) simulations. The effect of different manufacturing technologies is exemplified by two typical microwave substrates (AF45 and AI2O3). Furthermore, the impact of the uncertainties in the input quantities is investigated in such a way that conclusions for the design of CPWs as well as for the requirements on the accuracy of material measurement methods can be drawn.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512255
Umberto Paoletti, T. Hisakado, Osami Wada
The point-to-point partial self inductance of an infinite and perfectly conducting ground plane has been analytically calculated in closed form. The point-to-point mutual coupling between ground plane and a trace parallel to the ground plane has been expressed in terms of an integral, which should be solved numerically. The calculations are based on a new scalar potential directly related to the concept of partial inductances. Formulas for the conversion of partial inductances between the Lorenz's and Coulomb's gauges are also obtained. The definition of partial inductance in terms of the vector potential (e.g. in [1]) implicitly introduces equivalent circuits, where the voltage represents a difference of a scalar potential defined by the electric field and by the magnetic vector potential at the same time. Therefore, it should not surprise the possibility of having a partial inductance also on perfect ground planes. A part from the definition of the magnetic vector potential, the definition of ground plane partial inductance depends on the application, in particular on the considered current distribution on the ground plane. For example, in [2] the ground plane inductance is defined in terms of the induced current on the ground plane by a micro-strip conductor. In the present work, we will consider the current injected in one point and extracted from a second point on the ground plane, similarly to [3]. This type of partial inductance appears when there are connections to a ground plane, such as cables or micro-strip terminations. In a less proper way, it can be used for approximately representing the inductance related to the displacement current, when a micro-strip is decomposed in short segments carrying constant current. The numerical calculation of the point-to-point ground partial inductance is already considered in software of widespread use, such as FASTHENRY [4]. However, the segmentation of the ground plane can become a problem for configurations with high density of conductors [5]. The calculation time increases for larger ground planes, also because the image theory cannot be directly applied to the calculation of partial inductances.
{"title":"Analytical calculation of the point-to-point partial inductance of a perfect ground plane","authors":"Umberto Paoletti, T. Hisakado, Osami Wada","doi":"10.1109/SPI.2007.4512255","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512255","url":null,"abstract":"The point-to-point partial self inductance of an infinite and perfectly conducting ground plane has been analytically calculated in closed form. The point-to-point mutual coupling between ground plane and a trace parallel to the ground plane has been expressed in terms of an integral, which should be solved numerically. The calculations are based on a new scalar potential directly related to the concept of partial inductances. Formulas for the conversion of partial inductances between the Lorenz's and Coulomb's gauges are also obtained. The definition of partial inductance in terms of the vector potential (e.g. in [1]) implicitly introduces equivalent circuits, where the voltage represents a difference of a scalar potential defined by the electric field and by the magnetic vector potential at the same time. Therefore, it should not surprise the possibility of having a partial inductance also on perfect ground planes. A part from the definition of the magnetic vector potential, the definition of ground plane partial inductance depends on the application, in particular on the considered current distribution on the ground plane. For example, in [2] the ground plane inductance is defined in terms of the induced current on the ground plane by a micro-strip conductor. In the present work, we will consider the current injected in one point and extracted from a second point on the ground plane, similarly to [3]. This type of partial inductance appears when there are connections to a ground plane, such as cables or micro-strip terminations. In a less proper way, it can be used for approximately representing the inductance related to the displacement current, when a micro-strip is decomposed in short segments carrying constant current. The numerical calculation of the point-to-point ground partial inductance is already considered in software of widespread use, such as FASTHENRY [4]. However, the segmentation of the ground plane can become a problem for configurations with high density of conductors [5]. The calculation time increases for larger ground planes, also because the image theory cannot be directly applied to the calculation of partial inductances.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114850633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512194
A. Deutsch, H.H. Smith, C. Vakirtzis, J. Kozhaya, L.M. Greenberg
The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation and recommendations for CAD tool development are given.
{"title":"Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring","authors":"A. Deutsch, H.H. Smith, C. Vakirtzis, J. Kozhaya, L.M. Greenberg","doi":"10.1109/SPI.2007.4512194","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512194","url":null,"abstract":"The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation and recommendations for CAD tool development are given.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121558080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512213
B. Gustavsen
Residue perturbation (RP) is often used a means for enforcing passivity of rational models. One RP version combines a least squares problem with a constraints part and solves via quadratic programming (QP). A major difficulty is that commonly available QP solvers cannot utilize the problem sparsity, leading to lengthy computations. This paper proposes to take the eigenvalues of the residue matrices as free variables. This leads to a more compact problem and thus a fast computation (FRP). The resulting model error is found to be much smaller than when perturbing only the diagonal elements of the residue matrices. It is also shown how to combine the residue matrix eigenvalue perturbation with the recently developed modal perturbation approach (MP), leading to a fast version (FMP). The FMP/MP approaches have the additional advantage of retaining the relative accuracy of the admittance matrix eigenvalues.
{"title":"Fast passivity enforcement of rational macromodels by perturbation of residue matrix eigenvalues","authors":"B. Gustavsen","doi":"10.1109/SPI.2007.4512213","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512213","url":null,"abstract":"Residue perturbation (RP) is often used a means for enforcing passivity of rational models. One RP version combines a least squares problem with a constraints part and solves via quadratic programming (QP). A major difficulty is that commonly available QP solvers cannot utilize the problem sparsity, leading to lengthy computations. This paper proposes to take the eigenvalues of the residue matrices as free variables. This leads to a more compact problem and thus a fast computation (FRP). The resulting model error is found to be much smaller than when perturbing only the diagonal elements of the residue matrices. It is also shown how to combine the residue matrix eigenvalue perturbation with the recently developed modal perturbation approach (MP), leading to a fast version (FMP). The FMP/MP approaches have the additional advantage of retaining the relative accuracy of the admittance matrix eigenvalues.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123202117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512217
V. Ambalavanar, A. Jerome, P. Gunupudi
A new, accurate and efficient coupled interconnect simulation algorithm is presented in this paper. This algorithm eliminates redundancies present in simulation of interconnect networks by exploiting the repetitive nature of segments in traditional interconnect discretization methods with the aid of domain decomposition methods. Since the proposed algorithm does not perform any approximations, the numerical accuracy of the original network is not compromised. This algorithm was tested on practical interconnect networks and a considerable speed-up was obtained.
{"title":"Removing redundancy in interconnect simulation using domain decomposition techniques","authors":"V. Ambalavanar, A. Jerome, P. Gunupudi","doi":"10.1109/SPI.2007.4512217","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512217","url":null,"abstract":"A new, accurate and efficient coupled interconnect simulation algorithm is presented in this paper. This algorithm eliminates redundancies present in simulation of interconnect networks by exploiting the repetitive nature of segments in traditional interconnect discretization methods with the aid of domain decomposition methods. Since the proposed algorithm does not perform any approximations, the numerical accuracy of the original network is not compromised. This algorithm was tested on practical interconnect networks and a considerable speed-up was obtained.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512210
M. Voutilainen
The developed concept of ultra low power multi gigabit serial interface for mobile devices removes limits from mechanical design and device architectures. Power consumption of differential line drivers were reduced to 0.8 mW by lowering common-mode voltage of signals to 200 mV and using voltage source type drivers with 50-ohm output impedance to generate +-200 mV high-speed differential signal to receiver inputs. Lowering supply voltage to 200 mV and removing the parallel termination from receiver input are possible with voltage-source type driver when output impedance is matched to line impedance, providing additional 75% power saving without any change in receiver differential input signal. Zero idle power consumption of CMOS inverters makes them ideal single-ended drivers and receivers for short control messages using the same wires as high-speed drivers when no high-speed differential signaling is required.
{"title":"Future mobile device interconnections","authors":"M. Voutilainen","doi":"10.1109/SPI.2007.4512210","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512210","url":null,"abstract":"The developed concept of ultra low power multi gigabit serial interface for mobile devices removes limits from mechanical design and device architectures. Power consumption of differential line drivers were reduced to 0.8 mW by lowering common-mode voltage of signals to 200 mV and using voltage source type drivers with 50-ohm output impedance to generate +-200 mV high-speed differential signal to receiver inputs. Lowering supply voltage to 200 mV and removing the parallel termination from receiver input are possible with voltage-source type driver when output impedance is matched to line impedance, providing additional 75% power saving without any change in receiver differential input signal. Zero idle power consumption of CMOS inverters makes them ideal single-ended drivers and receivers for short control messages using the same wires as high-speed drivers when no high-speed differential signaling is required.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127713732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512256
J. Ravindra, M. Srinivas
For deep submicron (DSM) interconnects on-chip inductive effects are rising due to increasing clock speeds, decreasing interconnect lengths and signal rise times are the major concern for signal integrity and overall interconnect performance. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. For global wires inductance effects are more severe due to the lower resistance of these lines, which makes the reactive component of the wire impedance comparable to the resistive component, and also due to the presence of significant mutual inductive coupling between wires resulting from longer current return paths. This paper addresses an analytical model for inductive crosstalk for DSM technologies. Simulation results show that the effect of inductive coupling for long interconnects is significant but it is almost insignificant for local interconnects and the self inductance of the aggressor has more impact on crosstalk noise. All the simulations results carried out using Cadence's dynamic circuit simulator SPECTRE.
{"title":"Analytical crosstalk model with inductive coupling in VLSI interconnects","authors":"J. Ravindra, M. Srinivas","doi":"10.1109/SPI.2007.4512256","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512256","url":null,"abstract":"For deep submicron (DSM) interconnects on-chip inductive effects are rising due to increasing clock speeds, decreasing interconnect lengths and signal rise times are the major concern for signal integrity and overall interconnect performance. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. For global wires inductance effects are more severe due to the lower resistance of these lines, which makes the reactive component of the wire impedance comparable to the resistive component, and also due to the presence of significant mutual inductive coupling between wires resulting from longer current return paths. This paper addresses an analytical model for inductive crosstalk for DSM technologies. Simulation results show that the effect of inductive coupling for long interconnects is significant but it is almost insignificant for local interconnects and the self inductance of the aggressor has more impact on crosstalk noise. All the simulations results carried out using Cadence's dynamic circuit simulator SPECTRE.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126408343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512200
A. Maffucci, G. Miano, F. Villone
This paper addresses the problem of scaling interconnects to nanometric dimensions in future VLSI applications. Traditional copper interconnects are compared to innovative ones made by bundles of metallic carbon nanotubes. A new model is presented to describe propagation along CNT bundles, in the framework of the classical transmission line theory. A possible future scaled CNT bundle microstrip is analyzed and compared to a conventional microstrip.
{"title":"Comparison between metallic carbon nanotube and copper future VLSI nano-interconnects","authors":"A. Maffucci, G. Miano, F. Villone","doi":"10.1109/SPI.2007.4512200","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512200","url":null,"abstract":"This paper addresses the problem of scaling interconnects to nanometric dimensions in future VLSI applications. Traditional copper interconnects are compared to innovative ones made by bundles of metallic carbon nanotubes. A new model is presented to describe propagation along CNT bundles, in the framework of the classical transmission line theory. A possible future scaled CNT bundle microstrip is analyzed and compared to a conventional microstrip.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123761265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-05-13DOI: 10.1109/SPI.2007.4512233
K. Srinivasan, E. Engin, M. Swaminathan
Transient simulation using Laguerre polynomials is an unconditionally stable method, where the time-step is not limited by the fine resolution of the model. In this paper, a circuit model of the 3D FDTD grid for transient simulation using Laguerre polynomials has been derived. The circuit model enables FDTD simulation with Laguerre polynomials using the Spice MNA engine. In addition, circuit models help reduce the number of unknowns to be solved without the use of long cumbersome equations. Prior work suffer from the drawback of being able to simulate only for a certain time-duration. A method by which this limitation can be removed and accurate simulation can be carried out for all time has been outlined in this paper.
{"title":"Fast FDTD simulation of multiscale 3D models using laguerre-MNA","authors":"K. Srinivasan, E. Engin, M. Swaminathan","doi":"10.1109/SPI.2007.4512233","DOIUrl":"https://doi.org/10.1109/SPI.2007.4512233","url":null,"abstract":"Transient simulation using Laguerre polynomials is an unconditionally stable method, where the time-step is not limited by the fine resolution of the model. In this paper, a circuit model of the 3D FDTD grid for transient simulation using Laguerre polynomials has been derived. The circuit model enables FDTD simulation with Laguerre polynomials using the Spice MNA engine. In addition, circuit models help reduce the number of unknowns to be solved without the use of long cumbersome equations. Prior work suffer from the drawback of being able to simulate only for a certain time-duration. A method by which this limitation can be removed and accurate simulation can be carried out for all time has been outlined in this paper.","PeriodicalId":206352,"journal":{"name":"2007 IEEE Workshop on Signal Propagation on Interconnects","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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