A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown.<>
{"title":"Synthesis of easily testable sequential circuits with checking sequences","authors":"S. Shibatani, K. Kinoshita","doi":"10.1109/ATS.1992.224408","DOIUrl":"https://doi.org/10.1109/ATS.1992.224408","url":null,"abstract":"A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127722479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound.<>
{"title":"Test set compaction for combinational circuits","authors":"Jau-Shien Chang, Chen-Shang Lin","doi":"10.1109/ATS.1992.224429","DOIUrl":"https://doi.org/10.1109/ATS.1992.224429","url":null,"abstract":"Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115955921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present an approach to reduce the cost of test pattern generation of behavioral descriptions. This approach utilizes a group of methods allowing the designer to assess and to enhance the testability of behavioral descriptions.<>
{"title":"Methods to measure and to enhance the testability of behavioral descriptions of digital circuits","authors":"J. Santucci, G. Dray, M. Boumédine, N. Giambiasi","doi":"10.1109/ATS.1992.224448","DOIUrl":"https://doi.org/10.1109/ATS.1992.224448","url":null,"abstract":"The authors present an approach to reduce the cost of test pattern generation of behavioral descriptions. This approach utilizes a group of methods allowing the designer to assess and to enhance the testability of behavioral descriptions.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Compared to single signature analysis, checking multiple signatures yields smaller aliasing, easier fault coverage computation, shorter average test-time, and increased fault diagnosability. In conventional multiple signature (CMS) schemes, for a CUT to be declared good, at each check point, the signature obtained must match a specific reference. This strict one-to-one correspondence makes the CMS scheme complex to implement and expensive in terms of silicon area. The authors propose a fuzzy multiple signature compaction scheme in which the requirement for the one-to-one correspondence is removed. In the FMS scheme, for a CUT to be declared good, it suffices that the signature obtained at each check point correspond to any of a set of references.<>
{"title":"A fuzzy multiple signature compaction scheme for BIST","authors":"Yuejian Wu, A. Ivanov","doi":"10.1109/ATS.1992.224400","DOIUrl":"https://doi.org/10.1109/ATS.1992.224400","url":null,"abstract":"Compared to single signature analysis, checking multiple signatures yields smaller aliasing, easier fault coverage computation, shorter average test-time, and increased fault diagnosability. In conventional multiple signature (CMS) schemes, for a CUT to be declared good, at each check point, the signature obtained must match a specific reference. This strict one-to-one correspondence makes the CMS scheme complex to implement and expensive in terms of silicon area. The authors propose a fuzzy multiple signature compaction scheme in which the requirement for the one-to-one correspondence is removed. In the FMS scheme, for a CUT to be declared good, it suffices that the signature obtained at each check point correspond to any of a set of references.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126319482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a differential algorithm for concurrent simulation of path delay faults in sequential circuits. The simulator determines all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output, by analyzing vector-pairs and the hazard states occurring between vectors.<>
{"title":"Path delay fault simulation algorithms for sequential circuits","authors":"T. Chakraborty, V. Agrawal, M. Bushnell","doi":"10.1109/ATS.1992.224444","DOIUrl":"https://doi.org/10.1109/ATS.1992.224444","url":null,"abstract":"The authors present a differential algorithm for concurrent simulation of path delay faults in sequential circuits. The simulator determines all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output, by analyzing vector-pairs and the hazard states occurring between vectors.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134332088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors deal with some of the practical considerations that arise in porting ATPG patterns to the tester. Issues such as races, bidirectional pins, three-state buses and asynchronous circuits are discussed. Algorithm for dealing with these constructs during the test pattern generation phase are presented. Patterns that correctly handle such situations are easily ported to the tester. Experimental results on real circuits are presented. The results also include ATE resources such as tester time and memory required for the test program. The circuits are assumed to adhere to the CrossCheck design-for-testability methodology.<>
{"title":"Practical considerations in ATPG using CrossCheck technology","authors":"S. Chandra, N. Jacobson, G. Srinath","doi":"10.1109/ATS.1992.224441","DOIUrl":"https://doi.org/10.1109/ATS.1992.224441","url":null,"abstract":"The authors deal with some of the practical considerations that arise in porting ATPG patterns to the tester. Issues such as races, bidirectional pins, three-state buses and asynchronous circuits are discussed. Algorithm for dealing with these constructs during the test pattern generation phase are presented. Patterns that correctly handle such situations are easily ported to the tester. Experimental results on real circuits are presented. The results also include ATE resources such as tester time and memory required for the test program. The circuits are assumed to adhere to the CrossCheck design-for-testability methodology.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133590601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors deal with the design of a neural network which can be used to solve three-valued computer system diagnosis problems by using an integer linear programming approach. Simulation results show that neural nets are very effective for solving computer system diagnosis problems.<>
{"title":"Three-valued computer system diagnosis implemented by artificial neural network","authors":"Tinghuai Chen, Kaigui Wu, Yundi Wu","doi":"10.1109/ATS.1992.224410","DOIUrl":"https://doi.org/10.1109/ATS.1992.224410","url":null,"abstract":"The authors deal with the design of a neural network which can be used to solve three-valued computer system diagnosis problems by using an integer linear programming approach. Simulation results show that neural nets are very effective for solving computer system diagnosis problems.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131354440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor's pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<>
{"title":"A concurrent fault detection method for superscalar processors","authors":"A. Pawlovsky, M. Hanawa","doi":"10.1109/ATS.1992.224418","DOIUrl":"https://doi.org/10.1109/ATS.1992.224418","url":null,"abstract":"The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor's pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Random spot defects may result in discrete faults such as line breaks and short circuits. Therefore they could contribute significantly to yield losses in stable fabrication lines of VLSI integrated circuits. The authors show how to use laser based equipment to inject such faults at the circuit level. Experimental results carried out on 32 bits microprocessors are presented and point out one of the main applications of this approach: the test sequence improvement.<>
{"title":"Laser injection of spot defects on integrated circuits","authors":"R. Velazco, B. Martinet, G. Auvert","doi":"10.1109/ATS.1992.224415","DOIUrl":"https://doi.org/10.1109/ATS.1992.224415","url":null,"abstract":"Random spot defects may result in discrete faults such as line breaks and short circuits. Therefore they could contribute significantly to yield losses in stable fabrication lines of VLSI integrated circuits. The authors show how to use laser based equipment to inject such faults at the circuit level. Experimental results carried out on 32 bits microprocessors are presented and point out one of the main applications of this approach: the test sequence improvement.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131334260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test input vectors for ISCAS-85 benchmark circuits are derived, with which single faults of each signal line in the TTL combinational circuits can be detected by their quiescent supply currents. Also, they are compared with the vectors for fault detection methods on the primary output logic values. It is shown that by detecting faults with supply currents of TTL circuits, smaller size of test inputs can be derived for most of the circuits than fault detection methods based on the primary output logic values, and also, if both the output logic values and the supply current are used for detecting faults, the number of the test inputs can be reduced.<>
{"title":"Test input vectors for supply current testing of TTL combinational circuits","authors":"M. Hashizume, T. Tamesada, I. Tsukimoto","doi":"10.1109/ATS.1992.224436","DOIUrl":"https://doi.org/10.1109/ATS.1992.224436","url":null,"abstract":"Test input vectors for ISCAS-85 benchmark circuits are derived, with which single faults of each signal line in the TTL combinational circuits can be detected by their quiescent supply currents. Also, they are compared with the vectors for fault detection methods on the primary output logic values. It is shown that by detecting faults with supply currents of TTL circuits, smaller size of test inputs can be derived for most of the circuits than fault detection methods based on the primary output logic values, and also, if both the output logic values and the supply current are used for detecting faults, the number of the test inputs can be reduced.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134357040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：