The authors present a method to reduce test storage and test application time for stored-pattern testing in embedded full-scan circuits, without compromising the fault coverage. A combination of stored-pattern and built-in test is proposed to reduce the test storage and test application time by shifting output patterns back to the inputs of the circuit (similar to circular BIST), using the output responses of the circuit as additional test patterns. The circuit operates in such an autonomous mode as long as new faults can be detected. Externally applied, or stored, patterns are used to initialize the autonomous test application phase to maximize the fault coverage each phase achieves, and minimize the number of phases required.<>
{"title":"A test application scheme for embedded full-scan circuits to reduce testing costs","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1992.224407","DOIUrl":"https://doi.org/10.1109/ATS.1992.224407","url":null,"abstract":"The authors present a method to reduce test storage and test application time for stored-pattern testing in embedded full-scan circuits, without compromising the fault coverage. A combination of stored-pattern and built-in test is proposed to reduce the test storage and test application time by shifting output patterns back to the inputs of the circuit (similar to circular BIST), using the output responses of the circuit as additional test patterns. The circuit operates in such an autonomous mode as long as new faults can be detected. Externally applied, or stored, patterns are used to initialize the autonomous test application phase to maximize the fault coverage each phase achieves, and minimize the number of phases required.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116547820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a new concept: value difference, which is the difference of the faulty signal from the normal signal on a line, for fault simulation. Due to its saving of the event number, up to 41% saving of the simulation time is achieved. Both theoretical analysis and experimental result are provided.<>
{"title":"Fault simulation based on value difference","authors":"C. P. Wu, Chung-Len Lee, W. Shen","doi":"10.1109/ATS.1992.224431","DOIUrl":"https://doi.org/10.1109/ATS.1992.224431","url":null,"abstract":"The authors present a new concept: value difference, which is the difference of the faulty signal from the normal signal on a line, for fault simulation. Due to its saving of the event number, up to 41% saving of the simulation time is achieved. Both theoretical analysis and experimental result are provided.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Hatayama, T. Hayashi, M. Takakura, T. Suzuki, S. Michishita, H. Satoh
The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit.<>
{"title":"An approach to design-for-testability for memory embedding logic LSIs","authors":"K. Hatayama, T. Hayashi, M. Takakura, T. Suzuki, S. Michishita, H. Satoh","doi":"10.1109/ATS.1992.224406","DOIUrl":"https://doi.org/10.1109/ATS.1992.224406","url":null,"abstract":"The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127686877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the major objectives of research in VLSI circuit testing is to minimise the testing time and the associated overhead for test control. Sophisticated test scheduling algorithms have been proposed previously to reduce test application time. However, the cost of test control which constitutes a major part of the total test overhead has not received due attention. The authors propose a control constrained test scheduling approach. The cost of test control is evaluated based on the test controller hardware and the cost of test control signal distribution network. An algorithm has been designed to generate a schedule that minimises the combined cost of test application time and test control.<>
{"title":"A control constrained test scheduling approach for VLSI circuits","authors":"S. Misra, S. Subramanian, P. Chaudhuri","doi":"10.1109/ATS.1992.224417","DOIUrl":"https://doi.org/10.1109/ATS.1992.224417","url":null,"abstract":"One of the major objectives of research in VLSI circuit testing is to minimise the testing time and the associated overhead for test control. Sophisticated test scheduling algorithms have been proposed previously to reduce test application time. However, the cost of test control which constitutes a major part of the total test overhead has not received due attention. The authors propose a control constrained test scheduling approach. The cost of test control is evaluated based on the test controller hardware and the cost of test control signal distribution network. An algorithm has been designed to generate a schedule that minimises the combined cost of test application time and test control.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115086416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A strategy that reduces the memory usage to minimum is proposed and implemented. The results of implementation show that the dynamic memory usage of the concurrent fault simulator considered is indeed lower than other commonly used memory management strategies. It is shown through experimentation that the reduced memory usage improves substantially the performance of the concurrent fault simulator.<>
{"title":"Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits","authors":"K. Kim, K. Saluja","doi":"10.1109/ATS.1992.224433","DOIUrl":"https://doi.org/10.1109/ATS.1992.224433","url":null,"abstract":"A strategy that reduces the memory usage to minimum is proposed and implemented. The results of implementation show that the dynamic memory usage of the concurrent fault simulator considered is indeed lower than other commonly used memory management strategies. It is shown through experimentation that the reduced memory usage improves substantially the performance of the concurrent fault simulator.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129820681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice.<>
{"title":"Techniques for reducing hardware requirement of self checking combinational circuits","authors":"S. Pagey, S. Sherlekar, G. Venkatesh","doi":"10.1109/ATS.1992.224419","DOIUrl":"https://doi.org/10.1109/ATS.1992.224419","url":null,"abstract":"The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115865997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The behavior of break faults in PLAs is analyzed and a fault collapsing technique for the faults is presented. From the behavioral analysis, two patterns are needed to detect a break fault. By the fault collapsing technique, the number of break faults is reduced from 2*( Hash device)+( Hash output) to less than 2*( Hash input+ Hash product)+( Hash output). Experimental results show that, for 56 benchmarks, the number of break faults after fault collapsing is reduced to 18.37%.<>
{"title":"Break fault model and fault collapsing analysis for PLA's","authors":"Gwo-Haur Hwang, W. Shen","doi":"10.1109/ATS.1992.224412","DOIUrl":"https://doi.org/10.1109/ATS.1992.224412","url":null,"abstract":"The behavior of break faults in PLAs is analyzed and a fault collapsing technique for the faults is presented. From the behavioral analysis, two patterns are needed to detect a break fault. By the fault collapsing technique, the number of break faults is reduced from 2*( Hash device)+( Hash output) to less than 2*( Hash input+ Hash product)+( Hash output). Experimental results show that, for 56 benchmarks, the number of break faults after fault collapsing is reduced to 18.37%.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VLSI circuits are segmented using built-in self-test registers. During the test execution a signature is collected for each of the subcircuits. The author presents a set of test scheduling algorithms that minimize the hardware overhead required for test control and test evaluation under different restrictions. The subcircuit tests are ordered such that only a subset of the signatures must be scanned and evaluated at the end of the test. The algorithms allow a tradeoff between test time and test hardware overhead.<>
{"title":"Reducing BIST hardware by test schedule optimization","authors":"A. P. Stroele","doi":"10.1109/ATS.1992.224399","DOIUrl":"https://doi.org/10.1109/ATS.1992.224399","url":null,"abstract":"VLSI circuits are segmented using built-in self-test registers. During the test execution a signature is collected for each of the subcircuits. The author presents a set of test scheduling algorithms that minimize the hardware overhead required for test control and test evaluation under different restrictions. The subcircuit tests are ordered such that only a subset of the signatures must be scanned and evaluated at the end of the test. The algorithms allow a tradeoff between test time and test hardware overhead.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116661814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<>
{"title":"Behavioral design and test assistance for pipelined processors","authors":"H. Iwashita, T. Nakata, F. Hirose","doi":"10.1109/ATS.1992.224427","DOIUrl":"https://doi.org/10.1109/ATS.1992.224427","url":null,"abstract":"The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122261469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Assuming a stuck-at fault and stuck-open fault, the authors discussed a random current testing for CMOS logic circuits by monitoring a dynamic power supply current. Random patterns are generated using a modified LFSR, where the outputs of a CUT are fed back to an LFSR. This modification is intended for amplifying the influence of a fault near a primary outputs on the dynamic current. Simulation results showed that the modified LFSR works well for detectability, and a high fault coverage can be obtained applying a small number of test vectors.<>
{"title":"A current testing for CMOS logic circuits applying random patterns and monitoring dynamic power supply current","authors":"H. Tamamoto, H. Yokoyama, Y. Narita","doi":"10.1109/ATS.1992.224438","DOIUrl":"https://doi.org/10.1109/ATS.1992.224438","url":null,"abstract":"Assuming a stuck-at fault and stuck-open fault, the authors discussed a random current testing for CMOS logic circuits by monitoring a dynamic power supply current. Random patterns are generated using a modified LFSR, where the outputs of a CUT are fed back to an LFSR. This modification is intended for amplifying the influence of a fault near a primary outputs on the dynamic current. Simulation results showed that the modified LFSR works well for detectability, and a high fault coverage can be obtained applying a small number of test vectors.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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