Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232619
Wang Yuanchun, Man Weidong, Lv Changzhi, L. Zhiguo, Guo Chunsheng, Li Fei
Ever-increasing DC/DC power density and peak temperature challenge its reliability and performance. Thermal simulation and analysis play a significant role in development of new generation of DC/DC package design. This paper presents an accurate and fast approach to simulate the thermal distribution of a DC/DC module. The thermal distribution is simulated with ANSYS, and verified by infrared thermal images. This made feasible the thermal design to reduce stressing temperature peaks, so improving DC/DC reliability significantly.
{"title":"Thermal analysis of DC/DC module","authors":"Wang Yuanchun, Man Weidong, Lv Changzhi, L. Zhiguo, Guo Chunsheng, Li Fei","doi":"10.1109/IPFA.2009.5232619","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232619","url":null,"abstract":"Ever-increasing DC/DC power density and peak temperature challenge its reliability and performance. Thermal simulation and analysis play a significant role in development of new generation of DC/DC package design. This paper presents an accurate and fast approach to simulate the thermal distribution of a DC/DC module. The thermal distribution is simulated with ANSYS, and verified by infrared thermal images. This made feasible the thermal design to reduce stressing temperature peaks, so improving DC/DC reliability significantly.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232673
Chih-Hung Sun, Jyi-Tsong Lin, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, C. Kuo, Hsien-Nan Chiu
This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.
{"title":"Advanced block oxide MOSFETs for 25 nm technology node","authors":"Chih-Hung Sun, Jyi-Tsong Lin, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, C. Kuo, Hsien-Nan Chiu","doi":"10.1109/IPFA.2009.5232673","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232673","url":null,"abstract":"This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232648
L. Guoguang, Huang Yun, En Yunfei, Yang Shaohua, Lei Zhifeng
We report here the lifetime testing of 10 high power cm-bar arrays using an automated diode array reliability experiment. The devices are tested at 25°C/100A, with a pulse width of 200µs and a duty factor of 2%. Most devices survive more than 1.0×109 shots. Failure analysis results on the few failing devices reveal failure modes of mechanical stress, chemical contamination and thermal migration.
{"title":"Reliability of high power QCW cm-bar arrays","authors":"L. Guoguang, Huang Yun, En Yunfei, Yang Shaohua, Lei Zhifeng","doi":"10.1109/IPFA.2009.5232648","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232648","url":null,"abstract":"We report here the lifetime testing of 10 high power cm-bar arrays using an automated diode array reliability experiment. The devices are tested at 25°C/100A, with a pulse width of 200µs and a duty factor of 2%. Most devices survive more than 1.0×109 shots. Failure analysis results on the few failing devices reveal failure modes of mechanical stress, chemical contamination and thermal migration.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232575
Z. Tao, Hong-Xia Liu, Qianwei Kuang, Nai-Qiong Cai, H. Yue, Zhao Aaron, Tallavarjula Sai
The ultra-thin HfO2/SiO2 gate stack high-k dielectrics were deposited by Atomic Layer Deposition. The physical and structural properties of the HfO2/SiO2 films were investigated. Atomic force microscopy, transmission electron microscopy and x-ray reflectivity analysis results indicate that the atomic layer deposition can deposit HfO2/SiO2 gate stack dielectrics with good performance.
{"title":"Physical and structural properties of HfO2/SiO2 gate stack high-k dielectrics deposited by atomic layer deposition","authors":"Z. Tao, Hong-Xia Liu, Qianwei Kuang, Nai-Qiong Cai, H. Yue, Zhao Aaron, Tallavarjula Sai","doi":"10.1109/IPFA.2009.5232575","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232575","url":null,"abstract":"The ultra-thin HfO<inf>2</inf>/SiO<inf>2</inf> gate stack high-k dielectrics were deposited by Atomic Layer Deposition. The physical and structural properties of the HfO<inf>2</inf>/SiO<inf>2</inf> films were investigated. Atomic force microscopy, transmission electron microscopy and x-ray reflectivity analysis results indicate that the atomic layer deposition can deposit HfO<inf>2</inf>/SiO<inf>2</inf> gate stack dielectrics with good performance.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232711
M. Huo, K. Ding, Y. Han, S. Dong, X.Y. Du, D. Huang, B. Song
The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.
{"title":"Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device","authors":"M. Huo, K. Ding, Y. Han, S. Dong, X.Y. Du, D. Huang, B. Song","doi":"10.1109/IPFA.2009.5232711","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232711","url":null,"abstract":"The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122559064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232699
S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H. Kim, Y.W. Han, S. Kwon, Y. Oh
Scan chain failure analysis is more difficult and complicated compared to memory analysis and analysis of defect monitoring test element group (DTEG) which has a large area is also difficult. This paper has verified that various defects of logic process sub 65nm device are easily analyzed through Resistive Contrast Imaging (RCI) and nanoprobe. In addition, Metal5 (M5) bridge defect (Short case) was detected in failure of scan ATPG (Automatic Test Pattern Generation) which has long failing nets and by discovering Via4 (V4) open defect (Open case) by Unetch, it was confirmed that it is possible to analyze high resistance Via failure. And it was verified that position of Cu line void of metal7 (M7) can be localized at high level metal layer. It is judged that it will be used usefully in failure analysis sub 65nm in the future as a technique utilizing principle of RCI and nanoprobe and also it will make lots of contributions to improvement of yield.
扫描链失效分析相对于记忆分析和缺陷监测测试单元组(DTEG)的大面积分析更为困难和复杂。通过电阻对比成像(RCI)和纳米探针技术，验证了65nm以下器件逻辑工艺的各种缺陷是容易分析的。此外，在具有长失效网的扫描ATPG (Automatic Test Pattern Generation)故障中检测到Metal5 (M5)桥缺陷(Short case)，并通过Unetch发现Via4 (V4)开路缺陷(open case)，证实了分析高电阻过通故障的可能性。验证了金属7 (M7)的Cu线空洞位置可以定位在高能级金属层。认为它作为一种利用RCI原理和纳米探针的技术，将在65nm以下的失效分析中得到广泛应用，并对提高良率做出很大贡献。
{"title":"Logic failure analysis 65/45nm device using RCI & nano scale probe","authors":"S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H. Kim, Y.W. Han, S. Kwon, Y. Oh","doi":"10.1109/IPFA.2009.5232699","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232699","url":null,"abstract":"Scan chain failure analysis is more difficult and complicated compared to memory analysis and analysis of defect monitoring test element group (DTEG) which has a large area is also difficult. This paper has verified that various defects of logic process sub 65nm device are easily analyzed through Resistive Contrast Imaging (RCI) and nanoprobe. In addition, Metal5 (M5) bridge defect (Short case) was detected in failure of scan ATPG (Automatic Test Pattern Generation) which has long failing nets and by discovering Via4 (V4) open defect (Open case) by Unetch, it was confirmed that it is possible to analyze high resistance Via failure. And it was verified that position of Cu line void of metal7 (M7) can be localized at high level metal layer. It is judged that it will be used usefully in failure analysis sub 65nm in the future as a technique utilizing principle of RCI and nanoprobe and also it will make lots of contributions to improvement of yield.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123204929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232669
S. Toh, P. K. Tan, E. Hendarto, Q. Deng, H. Lin, Y. W. Goh, L. Zhu, H. Tan, Q.F. Wang, R. He, J. Lam, L. Hsia, Z. Mai
Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properties of NiSi. Ni spiking into Si substrate or conductive bridges between silicide on the gate electrodes and that on the source/drain terminals can occur. These effects can be induced or enhanced by stringent layout, stress or process conditions. Its impact can be evident from electrical failure analysis such as nanoprobing and C-AFM, that are useful in identifying the cause of failure.
{"title":"Electrical characteristics of leakage issues caused by defective Ni salicide","authors":"S. Toh, P. K. Tan, E. Hendarto, Q. Deng, H. Lin, Y. W. Goh, L. Zhu, H. Tan, Q.F. Wang, R. He, J. Lam, L. Hsia, Z. Mai","doi":"10.1109/IPFA.2009.5232669","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232669","url":null,"abstract":"Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properties of NiSi. Ni spiking into Si substrate or conductive bridges between silicide on the gate electrodes and that on the source/drain terminals can occur. These effects can be induced or enhanced by stringent layout, stress or process conditions. Its impact can be evident from electrical failure analysis such as nanoprobing and C-AFM, that are useful in identifying the cause of failure.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232564
L. Ji
This presentation gives a brief introduction for current topics discussed in Photovoltaics (PV) industry, especially by the international standard, testing and certification community. So far, the widely used standards are either deal with a design qualification and type approval (such as IEC 61215, IEC 61646), or module safety (such as IEC 61730, UL 1703). Some people in the PV community considered, or declared, that if the product passed these test, they are guaranteed for 20 years or more operation. These opinions are considered by many experts as not correct. For example, on IEC 61215, it specified that “The object of this test sequence is to determine the electrical and thermal characteristics of the module and to show, as far as is possible within reasonable constraints of cost and time, that the module is capable of withstanding prolonged exposure in climates described in the scope. The actual lifetime expectancy of modules so qualified will depend on their design, their environment and the conditions under which they are operated.” The presentation includes newly founded failures occurred on the real PV installations, their possible failure roots, suggested corrections, modifications on standard requirements and testing methods. In specific, the hot-spot endurance test, salt mist test, long term polymer material test, and UV exposal test will be discussed in details.
本报告简要介绍了当前光伏行业，特别是国际标准、测试和认证界讨论的主题。到目前为止，广泛使用的标准要么是处理设计资格和型式批准(如IEC 61215, IEC 61646)，要么是模块安全性(如IEC 61730, UL 1703)。光伏界的一些人认为，或者宣称，如果产品通过了这些测试，他们就可以保证20年或更长时间的运行。这些观点被许多专家认为是不正确的。例如，在IEC 61215中，它规定“该测试序列的目的是确定模块的电气和热特性，并在合理的成本和时间限制下尽可能地显示模块能够承受范围中描述的气候条件下的长时间暴露。”这些模块的实际寿命取决于它们的设计、使用环境和运行条件。”演讲内容包括在实际光伏安装中新发现的故障，可能的故障根源，建议的纠正，对标准要求和测试方法的修改。具体而言，将详细讨论热点耐久性测试、盐雾测试、长期高分子材料测试和紫外线暴露测试。
{"title":"Current topics on PV module and system reliability","authors":"L. Ji","doi":"10.1109/IPFA.2009.5232564","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232564","url":null,"abstract":"This presentation gives a brief introduction for current topics discussed in Photovoltaics (PV) industry, especially by the international standard, testing and certification community. So far, the widely used standards are either deal with a design qualification and type approval (such as IEC 61215, IEC 61646), or module safety (such as IEC 61730, UL 1703). Some people in the PV community considered, or declared, that if the product passed these test, they are guaranteed for 20 years or more operation. These opinions are considered by many experts as not correct. For example, on IEC 61215, it specified that “The object of this test sequence is to determine the electrical and thermal characteristics of the module and to show, as far as is possible within reasonable constraints of cost and time, that the module is capable of withstanding prolonged exposure in climates described in the scope. The actual lifetime expectancy of modules so qualified will depend on their design, their environment and the conditions under which they are operated.” The presentation includes newly founded failures occurred on the real PV installations, their possible failure roots, suggested corrections, modifications on standard requirements and testing methods. In specific, the hot-spot endurance test, salt mist test, long term polymer material test, and UV exposal test will be discussed in details.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232665
A. Deyine, K. Sanchez, P. Perdu, F. Bourcier, F. Battistella, F. Bereil, P. Le Nouy, D. Lewis, H. Deslandes
Laser Stimulation techniques are continuously developed in accordance with the apparition of new kind of defect. We propose the Full Dynamic La-ser Stimulation where the test is fully embedded in the localization process. By using a modulated laser instead of a continuous one we discriminate vectors fail in ad-dition to localization.
{"title":"Full Dynamic Laser simulation set up","authors":"A. Deyine, K. Sanchez, P. Perdu, F. Bourcier, F. Battistella, F. Bereil, P. Le Nouy, D. Lewis, H. Deslandes","doi":"10.1109/IPFA.2009.5232665","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232665","url":null,"abstract":"Laser Stimulation techniques are continuously developed in accordance with the apparition of new kind of defect. We propose the Full Dynamic La-ser Stimulation where the test is fully embedded in the localization process. By using a modulated laser instead of a continuous one we discriminate vectors fail in ad-dition to localization.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232634
F. He, Jun Wang, Zhiming Wu, Yadong Jiang, K. Yuan
The alignment system, as one of key component for stepper, developed rapidly in the last few years because of huge requirement on advanced exposing tools for VLSI and MEMS. Alignment accuracy is mainly affected by errors coming from mark deformations and optical system. In this paper, we combined mathematical model of Nikon stepper alignment optical system and analyzed alignment errors of Nikon stepper caused by mark deformation in different processes. The model was verified by different experiments. Finally some improvement process is put forward to enhance alignment accuracy.
{"title":"Analysis of alignment modeling for Nikon steppers","authors":"F. He, Jun Wang, Zhiming Wu, Yadong Jiang, K. Yuan","doi":"10.1109/IPFA.2009.5232634","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232634","url":null,"abstract":"The alignment system, as one of key component for stepper, developed rapidly in the last few years because of huge requirement on advanced exposing tools for VLSI and MEMS. Alignment accuracy is mainly affected by errors coming from mark deformations and optical system. In this paper, we combined mathematical model of Nikon stepper alignment optical system and analyzed alignment errors of Nikon stepper caused by mark deformation in different processes. The model was verified by different experiments. Finally some improvement process is put forward to enhance alignment accuracy.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126767659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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