Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232704
H. Lin, W. Shu
The use of scanning probe microscopes (SPM), such as conductive atomic force microscope (C-AFM) and scanning capacitance microscope (SCM) have been widely reported as a method of failure analysis in nanometer scale science and technology. This paper will demonstrate the use of the C-AFM to identify the true SRAM leakage path in CMOS process with the addition of a deep n-well (DNW) module. After taking electrical measurements, the SCM technique is utilized to identify and understand the physical root cause of the electrical failure.
{"title":"Using a combination of C-AFM and SCM for failure analysis of SRAM leakage in CMOS process with the addition of a DNW module","authors":"H. Lin, W. Shu","doi":"10.1109/IPFA.2009.5232704","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232704","url":null,"abstract":"The use of scanning probe microscopes (SPM), such as conductive atomic force microscope (C-AFM) and scanning capacitance microscope (SCM) have been widely reported as a method of failure analysis in nanometer scale science and technology. This paper will demonstrate the use of the C-AFM to identify the true SRAM leakage path in CMOS process with the addition of a deep n-well (DNW) module. After taking electrical measurements, the SCM technique is utilized to identify and understand the physical root cause of the electrical failure.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232597
Yanan Zhang, Lei Han
The bonding quality as obtained by strength tests of thermosonic bonding has been investigated as function of bonding temperature and ultrasonic power. The results show that bonding quality is very sensitive to process temperature and power. Optimum bonding temperature is not identical at different ultrasonic power. Analogously, optimum ultrasonic power which appears between 0.36W and 0.95W is not identical at different bonding temperature. The success rate of bonding is nearly 100% except for bonding temperature of 50°C and ultrasonic power of 0.035W. Meanwhile, their match is important. The combining influence of bonding temperature and power on bonding quality is analyzed by the interpolation of mean strength. The obtained data were useful for further researches.
{"title":"Combining influential analysis of bonding temperature and power on bonding quality","authors":"Yanan Zhang, Lei Han","doi":"10.1109/IPFA.2009.5232597","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232597","url":null,"abstract":"The bonding quality as obtained by strength tests of thermosonic bonding has been investigated as function of bonding temperature and ultrasonic power. The results show that bonding quality is very sensitive to process temperature and power. Optimum bonding temperature is not identical at different ultrasonic power. Analogously, optimum ultrasonic power which appears between 0.36W and 0.95W is not identical at different bonding temperature. The success rate of bonding is nearly 100% except for bonding temperature of 50°C and ultrasonic power of 0.035W. Meanwhile, their match is important. The combining influence of bonding temperature and power on bonding quality is analyzed by the interpolation of mean strength. The obtained data were useful for further researches.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232713
A.G. Street
Failure analysis tools and techniques have been evolving since engineers first took electronic components apart to see why they failed. First, using existing tools like optical microscopes, electrical test bench instruments and the machine shop to electrically and physically peer inside failed parts, failure analysts developed new methods, and later new tools to look inside electronic components and see physical structures and electrical signals. At the same time, the role failure analysis plays in the design and development cycle of systems and has expanded well beyond the original focus of quality and reliability.
{"title":"Failure analysis in the integrated fabless manufacturer (IFM) environment","authors":"A.G. Street","doi":"10.1109/IPFA.2009.5232713","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232713","url":null,"abstract":"Failure analysis tools and techniques have been evolving since engineers first took electronic components apart to see why they failed. First, using existing tools like optical microscopes, electrical test bench instruments and the machine shop to electrically and physically peer inside failed parts, failure analysts developed new methods, and later new tools to look inside electronic components and see physical structures and electrical signals. At the same time, the role failure analysis plays in the design and development cycle of systems and has expanded well beyond the original focus of quality and reliability.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127682623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232664
Jian-Hsing Lee, J. Shih, Shawn Guo, Dao-Hong Yang, Jone F. Chen, D. Su, Kenneth Wu
The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.
{"title":"The study of sensitive circuit and layout for CDM improvement","authors":"Jian-Hsing Lee, J. Shih, Shawn Guo, Dao-Hong Yang, Jone F. Chen, D. Su, Kenneth Wu","doi":"10.1109/IPFA.2009.5232664","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232664","url":null,"abstract":"The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121195132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232662
Wu Chunlei, L. Zhai, M. Motohiko, Jonathon Liu, H. Ma, John Liu
Failure analysis on advanced logic and mixed signal ICs more and more has to deal with so called ‘soft defect’. In this paper, a novel method to realize Soft Defect Localization (SDL) techniques without a synchronization signal for failure analysis is presented. We will present experimental results showing the accuracy of this method in order to help failure analysis to localize defect in short time.
{"title":"A Novel Method to Realize Soft Defect Localization Techniques without a Synchronization Signal for Failure Analysis","authors":"Wu Chunlei, L. Zhai, M. Motohiko, Jonathon Liu, H. Ma, John Liu","doi":"10.1109/IPFA.2009.5232662","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232662","url":null,"abstract":"Failure analysis on advanced logic and mixed signal ICs more and more has to deal with so called ‘soft defect’. In this paper, a novel method to realize Soft Defect Localization (SDL) techniques without a synchronization signal for failure analysis is presented. We will present experimental results showing the accuracy of this method in order to help failure analysis to localize defect in short time.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232584
R. Ding, Yintang Yang, Xingrong Ren, Xiaowen Xi, Bing Zhang
Based on density functional theory (DFT), the effect of boron (B) doping concentration on band gap of 3C-SiC is investigated. The analysis of density of states (DOS) and electron distribution indicates that the band gap tends to narrow with the increase of B concentration. The top of valence band, is contributed from B 2p level, and the bottom of conduction band, from B 2s in B-doped 3C-SiC. Both of them shift towards lower energy direction. With B concentration increases, the displacement of the bottom of conduction band is larger than that of the top of valence band, resulting in the narrowing of band gap. This result is useful for controlling band gap of doped 3C-SiC, and should be helpful for enhancing reliability and broadening the application ranges of SiC devices.
{"title":"First-principles study of boron doping-induced band gap narrowing in 3C-SiC","authors":"R. Ding, Yintang Yang, Xingrong Ren, Xiaowen Xi, Bing Zhang","doi":"10.1109/IPFA.2009.5232584","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232584","url":null,"abstract":"Based on density functional theory (DFT), the effect of boron (B) doping concentration on band gap of 3C-SiC is investigated. The analysis of density of states (DOS) and electron distribution indicates that the band gap tends to narrow with the increase of B concentration. The top of valence band, is contributed from B 2p level, and the bottom of conduction band, from B 2s in B-doped 3C-SiC. Both of them shift towards lower energy direction. With B concentration increases, the displacement of the bottom of conduction band is larger than that of the top of valence band, resulting in the narrowing of band gap. This result is useful for controlling band gap of doped 3C-SiC, and should be helpful for enhancing reliability and broadening the application ranges of SiC devices.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232657
Zou Xiao, Xu Jing-ping
Surface pretreatments with NO, N2O and NH3, are employed to prepare HfTiO/GeOxNy stack gate dielectric on n-Ge substrate. Impact of surface pretreatment on the electrical properties and reliability of the Ge MOS capacitors have been investigated. Excellent performances of Al/HfTiO/GeOxNy/n-Ge MOS capacitor with wet NO surface pretreatment have been achieved with an equivalent oxide thickness of 1.88 nm, physical thickness of 7.2 nm, equivalent permittivity of ∼ 34.5, interface -state density of 2.1×1011 eV−1cm−2, equivalent oxide charge of −7.64×1011 cm-2 and gate leakage current of 4.97×10−5 A/cm2 at Vg = 1 V. Experimental results also indicate that the wet NO surface pretreatment can lead to excellent reliability.
{"title":"Impacts of electrical properties and reliability on Ge MOS capacitors with surface pretreatment","authors":"Zou Xiao, Xu Jing-ping","doi":"10.1109/IPFA.2009.5232657","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232657","url":null,"abstract":"Surface pretreatments with NO, N<inf>2</inf>O and NH<inf>3</inf>, are employed to prepare HfTiO/GeOxNy stack gate dielectric on n-Ge substrate. Impact of surface pretreatment on the electrical properties and reliability of the Ge MOS capacitors have been investigated. Excellent performances of Al/HfTiO/GeOxNy/n-Ge MOS capacitor with wet NO surface pretreatment have been achieved with an equivalent oxide thickness of 1.88 nm, physical thickness of 7.2 nm, equivalent permittivity of ∼ 34.5, interface -state density of 2.1×10<sup>11</sup> eV<sup>−1</sup>cm<sup>−2</sup>, equivalent oxide charge of −7.64×10<sup>11</sup> cm-2 and gate leakage current of 4.97×10<sup>−5</sup> A/cm<sup>2</sup> at Vg = 1 V. Experimental results also indicate that the wet NO surface pretreatment can lead to excellent reliability.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114410903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232571
P. Chou, Ruchang Lin, T. Chen
The metal void information is very important for engineers to monitor the stability of the process and equipment during mass production and process tuning. However, traditional methods (X-S and P-V) are not efficient for metal void inspection. Therefore, the novel methodology is developed in this paper to provide a time efficient sample preparationm ethod and acceptable view region for plane-view metal void inspection instead of traditional methodology. This new approach involves the bevel polish technique and metal void inspection procedure. Thus the sample will be efficiently polished on a small slope and each layer could be inspected in the SEM simultaneously. By using this methodology can create a large inspection area for metal voids and dramatically reduce the cycle time of metal void inspection procedure to help engineers quickly get accurate metal void information.
{"title":"New approach: Sample preparation methodology for P-V metal void inspection","authors":"P. Chou, Ruchang Lin, T. Chen","doi":"10.1109/IPFA.2009.5232571","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232571","url":null,"abstract":"The metal void information is very important for engineers to monitor the stability of the process and equipment during mass production and process tuning. However, traditional methods (X-S and P-V) are not efficient for metal void inspection. Therefore, the novel methodology is developed in this paper to provide a time efficient sample preparationm ethod and acceptable view region for plane-view metal void inspection instead of traditional methodology. This new approach involves the bevel polish technique and metal void inspection procedure. Thus the sample will be efficiently polished on a small slope and each layer could be inspected in the SEM simultaneously. By using this methodology can create a large inspection area for metal voids and dramatically reduce the cycle time of metal void inspection procedure to help engineers quickly get accurate metal void information.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128113850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232730
H. Wang, C. Ng
The effect of hot carrier induced degradation on RF performance of InP/InGaAs double heterojunction bipolar transistors (DHBTs) is explored. Degradation of RF performance is more significant than that of DC performance. We found that the increase in base extrinsic resistance could be the root cause. A new degradation mechanism is proposed.
{"title":"Degradation of RF and noise characteristics of InP/InGaAs double heterojunction bipolar transistors under high reverse base-collector voltage","authors":"H. Wang, C. Ng","doi":"10.1109/IPFA.2009.5232730","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232730","url":null,"abstract":"The effect of hot carrier induced degradation on RF performance of InP/InGaAs double heterojunction bipolar transistors (DHBTs) is explored. Degradation of RF performance is more significant than that of DC performance. We found that the increase in base extrinsic resistance could be the root cause. A new degradation mechanism is proposed.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"39 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123522970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232596
A.-K. Tiedemann, M. Fakhri, R. Heiderhoff, J. Phang, L. Balk
Vertical and lateral Scanning Joule Expansion Microscopy measurements are compared for the first time. Frequency behaviors of the thermal-mechanical system are analyzed by introducing equivalent circuits for thermo-elastic transport mechanisms. Advanced failure analysis on degradation processes of interconnects can be performed by increasing temperature sensitivities and spatial resolutions.
{"title":"Advanced dynamic failure analysis on interconnects by vectorized Scanning Joule Expansion microscopy","authors":"A.-K. Tiedemann, M. Fakhri, R. Heiderhoff, J. Phang, L. Balk","doi":"10.1109/IPFA.2009.5232596","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232596","url":null,"abstract":"Vertical and lateral Scanning Joule Expansion Microscopy measurements are compared for the first time. Frequency behaviors of the thermal-mechanical system are analyzed by introducing equivalent circuits for thermo-elastic transport mechanisms. Advanced failure analysis on degradation processes of interconnects can be performed by increasing temperature sensitivities and spatial resolutions.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"33 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123538692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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