Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232587
Zhang Guangchen, F. Shiwei, Zhang Yuezong, Su Rong, Xie Xuesong, Ge Chenning
A novel method is proposed to evaluate the chip-level thermal non-uniformity of semiconductor devices by electrical transient thermal response testing. It is found that the degree of integrated chip thermal non-uniformity could be determined non-destructively by the device heating response curves.
{"title":"Study on the chip-level thermal non-uniformity evaluation of semiconductor devices","authors":"Zhang Guangchen, F. Shiwei, Zhang Yuezong, Su Rong, Xie Xuesong, Ge Chenning","doi":"10.1109/IPFA.2009.5232587","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232587","url":null,"abstract":"A novel method is proposed to evaluate the chip-level thermal non-uniformity of semiconductor devices by electrical transient thermal response testing. It is found that the degree of integrated chip thermal non-uniformity could be determined non-destructively by the device heating response curves.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114987627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232635
Yun-Xia Bai, Chun-sheng Guo, S. Feng, Kaikai Ding, Si-Xiang Zhuang, Rong Su
The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated the reliability and failure mechanism of power VDMOS. In constant-stress accelerated life test, the three different temperatures (150°C, 165°C and 180°C) are imposed on the devices. Under the bias VDS=7.5V, IDS=0.8A, and the channel temperature T=117°C, the average lifetime is 3.67×106 h , the activation energy E is 0.54eV, and the main failure mechanism is gate damage.
{"title":"Reliability evaluation of power VDMOSFET","authors":"Yun-Xia Bai, Chun-sheng Guo, S. Feng, Kaikai Ding, Si-Xiang Zhuang, Rong Su","doi":"10.1109/IPFA.2009.5232635","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232635","url":null,"abstract":"The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated the reliability and failure mechanism of power VDMOS. In constant-stress accelerated life test, the three different temperatures (150°C, 165°C and 180°C) are imposed on the devices. Under the bias VDS=7.5V, IDS=0.8A, and the channel temperature T=117°C, the average lifetime is 3.67×106 h , the activation energy E is 0.54eV, and the main failure mechanism is gate damage.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127483354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232646
R. Guan
A new type pressure sensor based on MEMS technology and the full oil cavity structure is developed in this paper, and the reliability of packaging process for sensor is researched, and its characteristics are measured. The experimental results demonstrate that the packaging materials and packaging process have all effect on reliability of the pressure sensor. By to coat a passivating layer on the chip can prevent effectively influence from the electric ions in silicone oil and improve obviously temperature stability of the pressure sensor. The using soft glue in die bonding process can diminish the sensor's zero point drift. The sensors resist fatigue characteristic and long reliability get be well resolved by bonding two golden wires. The systemic and all-around designing structure, reasonable selecting packaging material and optimize fabricating process can develop high quality the pressure sensor to meet requirements of the automobile environment.
{"title":"Packaging and reliability research on automobiles micro-pressure sensor","authors":"R. Guan","doi":"10.1109/IPFA.2009.5232646","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232646","url":null,"abstract":"A new type pressure sensor based on MEMS technology and the full oil cavity structure is developed in this paper, and the reliability of packaging process for sensor is researched, and its characteristics are measured. The experimental results demonstrate that the packaging materials and packaging process have all effect on reliability of the pressure sensor. By to coat a passivating layer on the chip can prevent effectively influence from the electric ions in silicone oil and improve obviously temperature stability of the pressure sensor. The using soft glue in die bonding process can diminish the sensor's zero point drift. The sensors resist fatigue characteristic and long reliability get be well resolved by bonding two golden wires. The systemic and all-around designing structure, reasonable selecting packaging material and optimize fabricating process can develop high quality the pressure sensor to meet requirements of the automobile environment.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125963029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232591
Zhong Ping, Chen-jie Song, N. Luo
Thermally induced stresses play a very important role in controlling the structural reliability of microchip packages. To address this issue, the shadow moiré interferometry is developed, which has been widely used in the field of observation for its real-time and high resolution. But how to extract the moiré fringes by using digital image processing method from a original Moiré fringe pattern is the key to accurate measurement of the warpage. The paper mainly concentrates on the method of effectively extracting the shadow moiré fringes from interference pattern produced by warpage of the PWB board and BGA package. Firstly, the low passing filtering and the dynamic threshold binarization proposed in this paper are applied to preprocess the moiré pattern. Then, the medial axis transformation and pruning algorithm applied to extract skeleton of moiré fringe have been put forward. Because the forficate fringes and noise fringes are main factors to affect precision of measurement, a effective main fringe extracting algorithm is proposed, which not only identifies and removes the forficate fringes and noise fringes from the main fringes, but also can connect the crack fringes which are hardly avoided after thinning operation. Finally, the information of warpage can be obtained from the location and orientation of moiré fringes. The three-dimensional delineation of detected object is resolved according to the moiré fringes extracted from shadow moiré pattern.
{"title":"Method of extracting high-resolution digital Moiré fringe in warpage measurement","authors":"Zhong Ping, Chen-jie Song, N. Luo","doi":"10.1109/IPFA.2009.5232591","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232591","url":null,"abstract":"Thermally induced stresses play a very important role in controlling the structural reliability of microchip packages. To address this issue, the shadow moiré interferometry is developed, which has been widely used in the field of observation for its real-time and high resolution. But how to extract the moiré fringes by using digital image processing method from a original Moiré fringe pattern is the key to accurate measurement of the warpage. The paper mainly concentrates on the method of effectively extracting the shadow moiré fringes from interference pattern produced by warpage of the PWB board and BGA package. Firstly, the low passing filtering and the dynamic threshold binarization proposed in this paper are applied to preprocess the moiré pattern. Then, the medial axis transformation and pruning algorithm applied to extract skeleton of moiré fringe have been put forward. Because the forficate fringes and noise fringes are main factors to affect precision of measurement, a effective main fringe extracting algorithm is proposed, which not only identifies and removes the forficate fringes and noise fringes from the main fringes, but also can connect the crack fringes which are hardly avoided after thinning operation. Finally, the information of warpage can be obtained from the location and orientation of moiré fringes. The three-dimensional delineation of detected object is resolved according to the moiré fringes extracted from shadow moiré pattern.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"53 61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122838309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232557
Yi-Lung Cheng, B. Wei, Yi-Lung Wang
Electromigration in Cu dual damascene interconnections has been investigated in terms of metal line width and thickness. The failure lifetime was found to decrease with decreasing line thickness and width. Furthermore, electromigration lifetime was greatly decreased as the line width was decreased to 0.07 m width. In addition to interface diffusion, the microstructure of Cu can be the dominant path for electromigraton mass transport. As a result, as the generation is scaled down to below 45 nm technology, electromigration behaviour will limit allowable current in the integrated circuit. In this study, the process improvement actions including the new copper surface passivation and bamboo-like Cu microstructure are presented and demonstrated an improvement electromigration performance.
{"title":"Scaling effect on electromigration in copper interconnects","authors":"Yi-Lung Cheng, B. Wei, Yi-Lung Wang","doi":"10.1109/IPFA.2009.5232557","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232557","url":null,"abstract":"Electromigration in Cu dual damascene interconnections has been investigated in terms of metal line width and thickness. The failure lifetime was found to decrease with decreasing line thickness and width. Furthermore, electromigration lifetime was greatly decreased as the line width was decreased to 0.07 m width. In addition to interface diffusion, the microstructure of Cu can be the dominant path for electromigraton mass transport. As a result, as the generation is scaled down to below 45 nm technology, electromigration behaviour will limit allowable current in the integrated circuit. In this study, the process improvement actions including the new copper surface passivation and bamboo-like Cu microstructure are presented and demonstrated an improvement electromigration performance.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128435512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232630
Qun Zhang, Grace Peng, Xia Gao, Craig Hamilton
Nowadays, with the development of silicon fabrication technology from 130um technology in early 70's till present 45nm technology, the geometries of transistors shrink smaller and smaller, IC devices become more sensitive to Electrostatic Discharge, or Electrical Overstress, i.e. ESD/EOS. ESD/EOS, therefore, is one of the major causes of device failures in the semiconductor industry. Tremendous efforts are being made by both component/ system level design and IC supplier / EMS/ OEM manufactory control. Failure analysis plays its unique role to validate ESD/EOS failure mechanism and drive the mitigation of ESD/EOS failures. In this paper, real case was stated to show the contribution of our FA results for ATE test program & IC circuit design debugging.
{"title":"Failure analysis of EOS damage case study","authors":"Qun Zhang, Grace Peng, Xia Gao, Craig Hamilton","doi":"10.1109/IPFA.2009.5232630","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232630","url":null,"abstract":"Nowadays, with the development of silicon fabrication technology from 130um technology in early 70's till present 45nm technology, the geometries of transistors shrink smaller and smaller, IC devices become more sensitive to Electrostatic Discharge, or Electrical Overstress, i.e. ESD/EOS. ESD/EOS, therefore, is one of the major causes of device failures in the semiconductor industry. Tremendous efforts are being made by both component/ system level design and IC supplier / EMS/ OEM manufactory control. Failure analysis plays its unique role to validate ESD/EOS failure mechanism and drive the mitigation of ESD/EOS failures. In this paper, real case was stated to show the contribution of our FA results for ATE test program & IC circuit design debugging.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232613
Y. Ye, J. Han, J. Li, G. Zhan, R. Zhu, F. Guo
According to the characterization of a new image sensor with quantum dots-quantum well (QDs-QW) hybrid hetero-structure, several electrostatic discharge (ESD) protection approaches for readout integrated circuits (ROIC) applied to novel image sensor with state-of-the-art CMOS technology were carefully designed. The results were presented and analyzed in this paper.
{"title":"Reliability analysis of ESD for novel image sensor with CMOS readout circuit","authors":"Y. Ye, J. Han, J. Li, G. Zhan, R. Zhu, F. Guo","doi":"10.1109/IPFA.2009.5232613","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232613","url":null,"abstract":"According to the characterization of a new image sensor with quantum dots-quantum well (QDs-QW) hybrid hetero-structure, several electrostatic discharge (ESD) protection approaches for readout integrated circuits (ROIC) applied to novel image sensor with state-of-the-art CMOS technology were carefully designed. The results were presented and analyzed in this paper.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123473168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232600
R. Portune, I. Kapilevich, H. Deslandes, R. Nicholson, L. Forli, M. Thétiot, S. Posson, B. Picart
We describe a wafer analysis methodology which uses test data, emission data and CAD data to accurately predict the location and type of defect. The methodology described enabled us to know the location with metal layer information and type of defect before performing destructive physical analysis.
{"title":"Enhanced wafer analysis using a combination of test, emission and software net tracing","authors":"R. Portune, I. Kapilevich, H. Deslandes, R. Nicholson, L. Forli, M. Thétiot, S. Posson, B. Picart","doi":"10.1109/IPFA.2009.5232600","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232600","url":null,"abstract":"We describe a wafer analysis methodology which uses test data, emission data and CAD data to accurately predict the location and type of defect. The methodology described enabled us to know the location with metal layer information and type of defect before performing destructive physical analysis.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114638924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232628
Jinglong Li, M. Motohiko, Winter Wang, J. Yu, G. Song
Sometimes failure analysis had to deal with the situation of the failure passing at room temperature but failing at high temperature, so that it was necessary to develop analyzing skills at high temperature. This paper introduced a special case fail at high temperature. By applying self heating method to obtain high temperature condition, the FA process of this case was described in detail. Finally the failure mechanism was demonstrated as well.
{"title":"Failure analysis of digital-analog mixed integrated circuit at high temperature","authors":"Jinglong Li, M. Motohiko, Winter Wang, J. Yu, G. Song","doi":"10.1109/IPFA.2009.5232628","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232628","url":null,"abstract":"Sometimes failure analysis had to deal with the situation of the failure passing at room temperature but failing at high temperature, so that it was necessary to develop analyzing skills at high temperature. This paper introduced a special case fail at high temperature. By applying self heating method to obtain high temperature condition, the FA process of this case was described in detail. Finally the failure mechanism was demonstrated as well.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121497221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232729
A. Alaeddine, M. Kadi, K. Daoud, B. Beydoun, D. Blavette
A new reliability study in SiGe Heterojunction Bipolar Transistors (HBTs) is investigated resulting from electromagnetic field aggression. We demonstrate experimental evidence of current gain degradation during electromagnetic stress. The device degradation is due to the Hot Carrier (HC) injected into the emitter- base spacer oxide, which induces Generation/Recombination trap centers, and leads to excess non-ideal base currents. Two-dimensional simulations, based on the HBT cross section, have been used to help understand the device physics associated with this degradation mechanism. As a consequence of introducing the surface recombination centers at the emitter-base spacer oxide, a non-ideal base current arises in agreement with the experimental data extracted. Simulation results show a strong correlation between stress time and recombination rate induced by the Si/SiO2 interface damage.
{"title":"Characterization and simulation of SiGe HBT degradation induced by electromagnetic field stress","authors":"A. Alaeddine, M. Kadi, K. Daoud, B. Beydoun, D. Blavette","doi":"10.1109/IPFA.2009.5232729","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232729","url":null,"abstract":"A new reliability study in SiGe Heterojunction Bipolar Transistors (HBTs) is investigated resulting from electromagnetic field aggression. We demonstrate experimental evidence of current gain degradation during electromagnetic stress. The device degradation is due to the Hot Carrier (HC) injected into the emitter- base spacer oxide, which induces Generation/Recombination trap centers, and leads to excess non-ideal base currents. Two-dimensional simulations, based on the HBT cross section, have been used to help understand the device physics associated with this degradation mechanism. As a consequence of introducing the surface recombination centers at the emitter-base spacer oxide, a non-ideal base current arises in agreement with the experimental data extracted. Simulation results show a strong correlation between stress time and recombination rate induced by the Si/SiO2 interface damage.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114771814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：