Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232737
A. Oates, M. H. Lin
The ever increasing demand for higher performance integrated circuits has led to the introduction of Cu / low-k interconnects. Electromigration failure of Cu interconnects is one of the major reliability concerns for circuits because dual damascene vias are inherently susceptible to void formation. Moreover, technology scaling leads to increased current carrying requirements, and this together with smaller critical geometries (i.e. smaller volumes of material associated with failure) presents an increasing challenge to ensure the long-term reliability of interconnects. The development of predictive models of via electromigration failure is an essential aspect of continued circuit reliability assurance. One significant challenge to the development of reliability models is the existence of multiple voiding modes in Cu vias. Development of accurate models requires a fundamental understanding of these voiding morphologies as a function of stress conditions, conductor geometry and processing, together with knowledge of void nucleation and growth kinetics.
{"title":"Modeling of Electromigration Failure Distribution of Cu Vias: Critical Current Density Effects and Reliability Extrapolation Procedures","authors":"A. Oates, M. H. Lin","doi":"10.1109/IPFA.2009.5232737","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232737","url":null,"abstract":"The ever increasing demand for higher performance integrated circuits has led to the introduction of Cu / low-k interconnects. Electromigration failure of Cu interconnects is one of the major reliability concerns for circuits because dual damascene vias are inherently susceptible to void formation. Moreover, technology scaling leads to increased current carrying requirements, and this together with smaller critical geometries (i.e. smaller volumes of material associated with failure) presents an increasing challenge to ensure the long-term reliability of interconnects. The development of predictive models of via electromigration failure is an essential aspect of continued circuit reliability assurance. One significant challenge to the development of reliability models is the existence of multiple voiding modes in Cu vias. Development of accurate models requires a fundamental understanding of these voiding morphologies as a function of stress conditions, conductor geometry and processing, together with knowledge of void nucleation and growth kinetics.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116507069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232578
Jinghua Jiang, D. He, Yongsheng Wang, M. Fu, B. Feng, Changbin Ju, Yu-fan Du
Ni-doped ZnO(ZnO:Ni)thin film had been studied widely as a ferromagnetic semiconductor, but there are far fewer studies on its infrared characteristics. This paper describes experiments in which Ni-doped ZnO thin films were deposited on quartz glass using a sol-gel process with different sintering temperatures. The infrared characteristics and the effects of the different fabrication processes were investigated using various techniques including X-ray diffraction (XRD), SEM and FT-IR.
{"title":"Infrared characteristics of ni-doped ZnO thin films","authors":"Jinghua Jiang, D. He, Yongsheng Wang, M. Fu, B. Feng, Changbin Ju, Yu-fan Du","doi":"10.1109/IPFA.2009.5232578","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232578","url":null,"abstract":"Ni-doped ZnO(ZnO:Ni)thin film had been studied widely as a ferromagnetic semiconductor, but there are far fewer studies on its infrared characteristics. This paper describes experiments in which Ni-doped ZnO thin films were deposited on quartz glass using a sol-gel process with different sintering temperatures. The infrared characteristics and the effects of the different fabrication processes were investigated using various techniques including X-ray diffraction (XRD), SEM and FT-IR.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232608
Guo Chunsheng, Bai Yunxia, Zhang Yuezong, Man Weidong, F. Shiwei, Lv Changzhi, L. Zhiguo
A novel method, which enables rapid determination of lifetime for semiconductor devices, is presented based on progressive-stress accelerated degradation test. Through two steps of acceleration: firstly, using process-stress accelerated test to accelerate the parameter degradation; secondly, using the data of 1∼5% degradation to extrapolate the data of 10∼50% degradation, this method shortens the test time to dozens or several hundreds of hours. To demonstrate the application of the method, a kind of mature products, Si PNP BJT 3CG120, was tested.
{"title":"A novel method for determing the lifetime of devices based on process-stress accelerated degradation test","authors":"Guo Chunsheng, Bai Yunxia, Zhang Yuezong, Man Weidong, F. Shiwei, Lv Changzhi, L. Zhiguo","doi":"10.1109/IPFA.2009.5232608","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232608","url":null,"abstract":"A novel method, which enables rapid determination of lifetime for semiconductor devices, is presented based on progressive-stress accelerated degradation test. Through two steps of acceleration: firstly, using process-stress accelerated test to accelerate the parameter degradation; secondly, using the data of 1∼5% degradation to extrapolate the data of 10∼50% degradation, this method shortens the test time to dozens or several hundreds of hours. To demonstrate the application of the method, a kind of mature products, Si PNP BJT 3CG120, was tested.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128477687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232626
Y. Liu, Ch. Y. Huang, N. N. Shan, C. Lu, G. Gao
In this paper, the failure mechanism of VDMOS in DC/DC converter was analyzed in detail. The result was gained by the reliability project that included reliability experiment and reliability analysis. The VDMOS devices were used in the circuit of DC/DC converter which can achieve the function of 28V into 15V. The accelerated life test was imposed on the VDMOS of the circuit, which has the temperature stress 5°C/day and the electrical stress. The test was began at 75°C, and the VDMOS devices failed at 215 °C. Then the failure analysis which recurred to the failure analysis tools such as the photon emission analysis (PEM) and the physical failure analysis (PFA) to the failed device showed the failure mechanism which is junction-break-down leakage inside source contact, under source wire bond. And the possible root cause of failure probably is Al spiking / diffusion into source contact causing junction leakage under reliability test condition of bias and temp. So in this way, the reliability of VDMOS in DC/DC converter can be tested and evaluated effectively.
{"title":"Failure analysis of VDMOS in DC/DC converter","authors":"Y. Liu, Ch. Y. Huang, N. N. Shan, C. Lu, G. Gao","doi":"10.1109/IPFA.2009.5232626","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232626","url":null,"abstract":"In this paper, the failure mechanism of VDMOS in DC/DC converter was analyzed in detail. The result was gained by the reliability project that included reliability experiment and reliability analysis. The VDMOS devices were used in the circuit of DC/DC converter which can achieve the function of 28V into 15V. The accelerated life test was imposed on the VDMOS of the circuit, which has the temperature stress 5°C/day and the electrical stress. The test was began at 75°C, and the VDMOS devices failed at 215 °C. Then the failure analysis which recurred to the failure analysis tools such as the photon emission analysis (PEM) and the physical failure analysis (PFA) to the failed device showed the failure mechanism which is junction-break-down leakage inside source contact, under source wire bond. And the possible root cause of failure probably is Al spiking / diffusion into source contact causing junction leakage under reliability test condition of bias and temp. So in this way, the reliability of VDMOS in DC/DC converter can be tested and evaluated effectively.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232717
Dapeng Zhou, Mingxiang Wang, Meng Zhang, Han Hao, Dongli Zhang, M. Wong
Anomalous “sweeping stress” induced degradation is first observed in n-type metal-induced laterally crystallized low temperature thin film transistors (TFTs). Key stress parameters include the maximum drain bias, the sweeping time and the number of sweeping. Degradation occurs only when the maximum drain bias exceeds a critical value. Both transfer and output characteristic degradation is found much similar to that of hot carrier (HC) degradation. But longer sweeping time causes larger degradation, which is opposite to that in dynamic HC degradation. Besides, such degradation can only be observed in low temperature crystallized TFTs.
{"title":"Anomalous “sweeping stress” induced degradation in n-type low temperature poly-Si thin film transistors","authors":"Dapeng Zhou, Mingxiang Wang, Meng Zhang, Han Hao, Dongli Zhang, M. Wong","doi":"10.1109/IPFA.2009.5232717","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232717","url":null,"abstract":"Anomalous “sweeping stress” induced degradation is first observed in n-type metal-induced laterally crystallized low temperature thin film transistors (TFTs). Key stress parameters include the maximum drain bias, the sweeping time and the number of sweeping. Degradation occurs only when the maximum drain bias exceeds a critical value. Both transfer and output characteristic degradation is found much similar to that of hot carrier (HC) degradation. But longer sweeping time causes larger degradation, which is opposite to that in dynamic HC degradation. Besides, such degradation can only be observed in low temperature crystallized TFTs.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232672
A. Machouat, G. Haller, V. Goubier, D. Lewis, P. Perdu, V. Pouget, F. Essely
The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.
{"title":"Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique","authors":"A. Machouat, G. Haller, V. Goubier, D. Lewis, P. Perdu, V. Pouget, F. Essely","doi":"10.1109/IPFA.2009.5232672","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232672","url":null,"abstract":"The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122982546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232715
Young Sun, Mark Zhang, Jossen Yu, W. Dong, W. Chien
A full-flow failure analysis (FA) was introduced in this paper. From the FA, we resolved odd/ even word-line failure which lead to poor endurance performance of a NAND Flash. After removing this defect, the endurance performance of this NAND Flash is greatly enhanced.
{"title":"Failure analysis of odd/even word-line failure to improve the endurance performance of a NAND Flash","authors":"Young Sun, Mark Zhang, Jossen Yu, W. Dong, W. Chien","doi":"10.1109/IPFA.2009.5232715","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232715","url":null,"abstract":"A full-flow failure analysis (FA) was introduced in this paper. From the FA, we resolved odd/ even word-line failure which lead to poor endurance performance of a NAND Flash. After removing this defect, the endurance performance of this NAND Flash is greatly enhanced.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126270667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232733
R. L. de Orio, H. Ceric, J. Červenka, S. Selberherr
In this work we analyze the influence of the statistical distribution of copper grain sizes on the electromigration time to failure distribution based on numerical simulations. We have applied a continuum multi-physics electromigration model which incorporates the effects of grain boundaries for stress build-up. It is shown that the lognormal distribution of grain sizes causes a lognormal distribution for the times to failure. Moreover, the increase of the standard deviation of the grain size distribution results in an increase of the electromigration lifetimes standard deviation.
{"title":"The effect of microstructure on the electromigration lifetime distribution","authors":"R. L. de Orio, H. Ceric, J. Červenka, S. Selberherr","doi":"10.1109/IPFA.2009.5232733","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232733","url":null,"abstract":"In this work we analyze the influence of the statistical distribution of copper grain sizes on the electromigration time to failure distribution based on numerical simulations. We have applied a continuum multi-physics electromigration model which incorporates the effects of grain boundaries for stress build-up. It is shown that the lognormal distribution of grain sizes causes a lognormal distribution for the times to failure. Moreover, the increase of the standard deviation of the grain size distribution results in an increase of the electromigration lifetimes standard deviation.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232696
Jyi-Tsong Lin, C. Kuo, Tai-Yi Lee, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu
We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.
{"title":"Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate","authors":"Jyi-Tsong Lin, C. Kuo, Tai-Yi Lee, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu","doi":"10.1109/IPFA.2009.5232696","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232696","url":null,"abstract":"We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232705
H. Lin, Randy Wang
The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes the use of nanoprobing and scanning electron microscope (SEM) doping contrast techniques to quickly and precisely pinpoint the leakage path.
{"title":"Using nanoprobing and SEM doping contrast techniques for failure analysis of current leakage in CMOS HV technology","authors":"H. Lin, Randy Wang","doi":"10.1109/IPFA.2009.5232705","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232705","url":null,"abstract":"The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes the use of nanoprobing and scanning electron microscope (SEM) doping contrast techniques to quickly and precisely pinpoint the leakage path.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114325630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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