Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232565
C.Z. Zhao, M. Werner, S. Taylor, P. Chalker, R. Potter, J. Gaskell
Radiation-induced degradation of HfO2, ZrO2, LaAlO3, and NdAlO3 thin films was studied and compared based on a Fe55 X-ray source and Cs137 γ-ray source. After the X-ray exposure of a total dose of 100krad, negative VFB shifts were observed in these thin films, whereas after the γ-ray exposures of the same dose, positive VFB shifts was observed.
{"title":"High-k dielectrics' radiation response to X-ray and γ-ray exposure","authors":"C.Z. Zhao, M. Werner, S. Taylor, P. Chalker, R. Potter, J. Gaskell","doi":"10.1109/IPFA.2009.5232565","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232565","url":null,"abstract":"Radiation-induced degradation of HfO<inf>2</inf>, ZrO<inf>2</inf>, LaAlO<inf>3</inf>, and NdAlO<inf>3</inf> thin films was studied and compared based on a Fe<sup>55</sup> X-ray source and Cs<sup>137</sup> γ-ray source. After the X-ray exposure of a total dose of 100krad, negative VFB shifts were observed in these thin films, whereas after the γ-ray exposures of the same dose, positive VFB shifts was observed.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125447599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232695
E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley
The electrical behavior of broken down thin films of magnesium oxide (MgO) grown on indium phosphide (InP) substrates was investigated. To our knowledge, this is the first report that identifies the Soft Break Down (SBD) conduction mode in a metal gate/high-κ/III–V semiconductor structure. It is shown that the leakage current associated with this failure mode follows the power-law model I=aVb for both injection polarities in a voltage range that largely exceeds the one reported for SiO2. We also show that the Hard Break Down (HBD) current is remarkably high, involving significant thermal effects that are believed to be at the origin of the switching behavior exhibited by the I–V characteristics.
{"title":"Post-breakdown conduction in metal gate/MgO/InP structures","authors":"E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley","doi":"10.1109/IPFA.2009.5232695","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232695","url":null,"abstract":"The electrical behavior of broken down thin films of magnesium oxide (MgO) grown on indium phosphide (InP) substrates was investigated. To our knowledge, this is the first report that identifies the Soft Break Down (SBD) conduction mode in a metal gate/high-κ/III–V semiconductor structure. It is shown that the leakage current associated with this failure mode follows the power-law model I=aVb for both injection polarities in a voltage range that largely exceeds the one reported for SiO2. We also show that the Hard Break Down (HBD) current is remarkably high, involving significant thermal effects that are believed to be at the origin of the switching behavior exhibited by the I–V characteristics.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232698
E. Wu, J. Suñé
In this paper, the advances in the understanding of breakdown statistics and physics of the so-called first breakdown (BD) phenomena are presented. Then the recent findings on post-breakdown effects and the impact of oxide BD on device failure and circuit functionality are reviewed. With this state-of-the-art understanding of the first BD methodology and post-BD methodologies, a robust reliability projection methodology can be developed for SiO2-based dielectrics which covers a wide range of oxide thicknesses and applied voltages. Furthermore, these advances will allow the development of a viable circuit-level reliability assessment methodology from basic breakdown physics.
{"title":"Towards a viable TDDB reliability assessment methodology: From breakdown physics to circuit failure","authors":"E. Wu, J. Suñé","doi":"10.1109/IPFA.2009.5232698","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232698","url":null,"abstract":"In this paper, the advances in the understanding of breakdown statistics and physics of the so-called first breakdown (BD) phenomena are presented. Then the recent findings on post-breakdown effects and the impact of oxide BD on device failure and circuit functionality are reviewed. With this state-of-the-art understanding of the first BD methodology and post-BD methodologies, a robust reliability projection methodology can be developed for SiO2-based dielectrics which covers a wide range of oxide thicknesses and applied voltages. Furthermore, these advances will allow the development of a viable circuit-level reliability assessment methodology from basic breakdown physics.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122578050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232618
Weibin Wang
In this paper, an E-D-search-based algorithm is proposed to minimize power consumption with resources operating at multiple voltages under the timing constraints. The inputs to the algorithm consist of a data flow graph (DFG) representation of a circuit, the timing constraints, and a design library with fully characterized resources. Experimental results with a number of DSP benchmarks show that the algorithm can achieve significant power reduction.
{"title":"A low power scheduling methodology under the timing constraints","authors":"Weibin Wang","doi":"10.1109/IPFA.2009.5232618","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232618","url":null,"abstract":"In this paper, an E-D-search-based algorithm is proposed to minimize power consumption with resources operating at multiple voltages under the timing constraints. The inputs to the algorithm consist of a data flow graph (DFG) representation of a circuit, the timing constraints, and a design library with fully characterized resources. Experimental results with a number of DSP benchmarks show that the algorithm can achieve significant power reduction.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116086483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232548
Yuqi Jiang, Xianzhong Song, Song Ye, Mingxiang Wang
Frameless thin film photovoltaic module is mounted to metal rails by acrylic tape. Theoretical and FEA simulation show that the bonded rail mounting configuration can be modeled as beam series consisting of cantilever beams and fixed-fixed beams. A design rule was found for the relationship between tape-to-tape spacing and tape to glass edge spacing. The optimized mounting solutions were obtained from seven tape patterns, for the purpose of low stress mounting, higher vibration natural frequency, and low cost.
{"title":"Optimization of bonded rail mounting for thin film PV modules","authors":"Yuqi Jiang, Xianzhong Song, Song Ye, Mingxiang Wang","doi":"10.1109/IPFA.2009.5232548","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232548","url":null,"abstract":"Frameless thin film photovoltaic module is mounted to metal rails by acrylic tape. Theoretical and FEA simulation show that the bonded rail mounting configuration can be modeled as beam series consisting of cantilever beams and fixed-fixed beams. A design rule was found for the relationship between tape-to-tape spacing and tape to glass edge spacing. The optimized mounting solutions were obtained from seven tape patterns, for the purpose of low stress mounting, higher vibration natural frequency, and low cost.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116715079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232654
Yinchao Chen, Shuhui Yang
In this paper, we extend the mixed mode S-parameter representation and its properties for a differential network commonly used in integrated circuits and printed circuit boards (PCBs). As an example of a differential network circuit, we illustrate the analysis of a pair of differential traces printed on a PCB using Ansoft HFSS to simulate the S-parameters. The differential pair is a typical transmission line that includes interconnects (vias) and is routed between PCB chip dies. Then we construct a differential schematic circuit using the simulated S-parameters of the PCB traces, and extract its associated Rx voltage signals and eye diagram.
{"title":"Mixed mode S-parameters analysis for differential networks in integrated circuits","authors":"Yinchao Chen, Shuhui Yang","doi":"10.1109/IPFA.2009.5232654","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232654","url":null,"abstract":"In this paper, we extend the mixed mode S-parameter representation and its properties for a differential network commonly used in integrated circuits and printed circuit boards (PCBs). As an example of a differential network circuit, we illustrate the analysis of a pair of differential traces printed on a PCB using Ansoft HFSS to simulate the S-parameters. The differential pair is a typical transmission line that includes interconnects (vias) and is routed between PCB chip dies. Then we construct a differential schematic circuit using the simulated S-parameters of the PCB traces, and extract its associated Rx voltage signals and eye diagram.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232583
Y. Cheng, T. Li, H. Li, D. Jing
Mesocarbon microbeads (MCMB) were prepared by heating a medium coal tar pitch at 420 °C for 2 hours, with the P-toluene sulphonic acid (PTSA) and the phenyl silicone oil as the catalyst and the reaction medium respectively. After the oxidative stabilization of MCMB, the oxygen content and the number of functional groups are increased, while the micro-crystal structures become worse. However, after the successive carbonization and graphitization, the oxygen content and the number of functional groups are decreased, the micro-crystal structures become well, and the yields are decreased.
{"title":"Preparation of mesocarbon microbeads and microstructure evolution","authors":"Y. Cheng, T. Li, H. Li, D. Jing","doi":"10.1109/IPFA.2009.5232583","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232583","url":null,"abstract":"Mesocarbon microbeads (MCMB) were prepared by heating a medium coal tar pitch at 420 °C for 2 hours, with the P-toluene sulphonic acid (PTSA) and the phenyl silicone oil as the catalyst and the reaction medium respectively. After the oxidative stabilization of MCMB, the oxygen content and the number of functional groups are increased, while the micro-crystal structures become worse. However, after the successive carbonization and graphitization, the oxygen content and the number of functional groups are decreased, the micro-crystal structures become well, and the yields are decreased.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128047738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232738
Y. Tong, Y. K. Lim, C.Q. Chen, W.Y. Zhang, J.B. Tan, D. Sohn, L. Hsia
A novel industry methodology has been developed to analyze TDDB reliability failure on Cu/Low-k SiCOH interconnects. Initial breakdown point is at interface between capping layer and metal line. Inline process control needs to be tightened to improve end of line profile and electric field variation.
{"title":"A novel methodology to analyze time-dependent dielectric breakdown failure mechanism of copper/low-k interconnects","authors":"Y. Tong, Y. K. Lim, C.Q. Chen, W.Y. Zhang, J.B. Tan, D. Sohn, L. Hsia","doi":"10.1109/IPFA.2009.5232738","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232738","url":null,"abstract":"A novel industry methodology has been developed to analyze TDDB reliability failure on Cu/Low-k SiCOH interconnects. Initial breakdown point is at interface between capping layer and metal line. Inline process control needs to be tightened to improve end of line profile and electric field variation.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"922 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133107711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232667
Lim Soon Huat, Sun Wanxin, V. Narang, J. Chin
This paper demonstrates the Veeco heating stage for high temperature Conductive-AFM analysis which is very useful for revealing leaky contacts associated with soft failures. CAFM at 80°C is performed on SOI transistors to isolate leaky polysilicon gate contacts. Nanoprobing at high temperature is performed and it shows strong correlation with the high temperature CAFM data. High temperature CAFM helped to isolate higher gate oxide leakage current in the failing transistor in SRAM memory cell.
{"title":"High-temperature Conductive-AFM technique for resolution of soft failures","authors":"Lim Soon Huat, Sun Wanxin, V. Narang, J. Chin","doi":"10.1109/IPFA.2009.5232667","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232667","url":null,"abstract":"This paper demonstrates the Veeco heating stage for high temperature Conductive-AFM analysis which is very useful for revealing leaky contacts associated with soft failures. CAFM at 80°C is performed on SOI transistors to isolate leaky polysilicon gate contacts. Nanoprobing at high temperature is performed and it shows strong correlation with the high temperature CAFM data. High temperature CAFM helped to isolate higher gate oxide leakage current in the failing transistor in SRAM memory cell.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133802791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-06DOI: 10.1109/IPFA.2009.5232732
Lei Wang, Zhenqing Zhao, Jianhui Wang, L. Wen, Qian Wang, Jaisung Lee
This paper gives a detailed investigation on TSOP warpage mechanism. The influences of all the factors on warpage behavior, including materials (EMC ingredient and lead frame), lead frame design and assembly process, were investigated through numerical simulation and experimental study. The simulation result showed that low CTE material is a good choice for warpage reduction. And it also indicated that by properly modifying the lead frame design, the warpage performance can be improved. Much attention was paid to the curing process as this thermal process would obviously affect the stress formation and release in the package. It was deduced that a reduction in the cooling rate above Tg during cure would reduce warpage based on theoretical thermal analysis, and the experiment result proved it did work. Finally a modification to the cure process is proposed as the most cost effective and practicable solution in actual production.
{"title":"Investigation on TSOP warpage mechanism and improvement method","authors":"Lei Wang, Zhenqing Zhao, Jianhui Wang, L. Wen, Qian Wang, Jaisung Lee","doi":"10.1109/IPFA.2009.5232732","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232732","url":null,"abstract":"This paper gives a detailed investigation on TSOP warpage mechanism. The influences of all the factors on warpage behavior, including materials (EMC ingredient and lead frame), lead frame design and assembly process, were investigated through numerical simulation and experimental study. The simulation result showed that low CTE material is a good choice for warpage reduction. And it also indicated that by properly modifying the lead frame design, the warpage performance can be improved. Much attention was paid to the curing process as this thermal process would obviously affect the stress formation and release in the package. It was deduced that a reduction in the cooling rate above Tg during cure would reduce warpage based on theoretical thermal analysis, and the experiment result proved it did work. Finally a modification to the cure process is proposed as the most cost effective and practicable solution in actual production.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134359210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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