Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559670
Shabnam Khomejani, A. Movaghar
For increasing safety of driving, intelligent vehicles in vehicular ad hoc networks (VANETs) communicate with each other by sending announcements. The existence of a system that guarantees the trustworthiness of these announcements seems necessary. The proposed approach generating announcements should be preserved from internal and external attackers that attempt to send fake messages. In this paper, we use a group-based endorsement mechanism based on threshold signatures against internal attackers. We choose NTRUSign as a public key cryptosystem for decreasing signature generation and verification times. This approach optimizes the network overhead and consequently its performance. In this scheme, also the privacy of signers and endorsers that generate or endorse trustworthy announcements is preserved.
{"title":"Privacy consideration for trustworthy vehicular ad hoc networks","authors":"Shabnam Khomejani, A. Movaghar","doi":"10.1109/ICEIE.2010.5559670","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559670","url":null,"abstract":"For increasing safety of driving, intelligent vehicles in vehicular ad hoc networks (VANETs) communicate with each other by sending announcements. The existence of a system that guarantees the trustworthiness of these announcements seems necessary. The proposed approach generating announcements should be preserved from internal and external attackers that attempt to send fake messages. In this paper, we use a group-based endorsement mechanism based on threshold signatures against internal attackers. We choose NTRUSign as a public key cryptosystem for decreasing signature generation and verification times. This approach optimizes the network overhead and consequently its performance. In this scheme, also the privacy of signers and endorsers that generate or endorse trustworthy announcements is preserved.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115148363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559727
K. Sarawadekar, S. Banerjee
With the growth in multimedia technology, demand for highspeed real time image compression system has also increased. JPEG 2000 standard is developed to cater such application requirements. However, the sequential execution of the bit plane coder (BPC) used in this standard consumes more clock cycles. To improve the performance of the BPC, a new concurrent context modeling technique is proposed in this paper. To study number of context generated in each clock cycle, analysis is carried out on five ISO grayscale images with size 512 × 512. The study revealed that about 58% of time more than 4 contexts are generated in one clock. Therefore, a new concurrent context coding architecture is proposed in this paper. It is implemented on Startix FPGA and the hardware requirement is reduced significantly, compared to similar architectures. Moreover, number of clock cycles required to encode a bit plane is reduced by 10% and it is minimum 2.5 times faster than the similar designs in existence. This design operates at 164.47 MHz, which makes it compatible for encoding HDTV 1920 × 1080 4:2:2 at 39 frames per second.
{"title":"Area efficient, high-speed VLSI design for EBCOT block coder in JPEG 2000","authors":"K. Sarawadekar, S. Banerjee","doi":"10.1109/ICEIE.2010.5559727","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559727","url":null,"abstract":"With the growth in multimedia technology, demand for highspeed real time image compression system has also increased. JPEG 2000 standard is developed to cater such application requirements. However, the sequential execution of the bit plane coder (BPC) used in this standard consumes more clock cycles. To improve the performance of the BPC, a new concurrent context modeling technique is proposed in this paper. To study number of context generated in each clock cycle, analysis is carried out on five ISO grayscale images with size 512 × 512. The study revealed that about 58% of time more than 4 contexts are generated in one clock. Therefore, a new concurrent context coding architecture is proposed in this paper. It is implemented on Startix FPGA and the hardware requirement is reduced significantly, compared to similar architectures. Moreover, number of clock cycles required to encode a bit plane is reduced by 10% and it is minimum 2.5 times faster than the similar designs in existence. This design operates at 164.47 MHz, which makes it compatible for encoding HDTV 1920 × 1080 4:2:2 at 39 frames per second.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123040388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559665
Gao Tingting, Sun Bin
Along with the developments of the high-speed railway, higher and higher technical requirements for the high-speed railway mobile communication system are raised. Since the “Global System for Mobile Communications Railways” (GSM-R) implemented today is based on GSM, the new technology in GSM evolution can be used in the highspeed railway mobile communication system to adapt to the new requirements. This paper introduces a high-speed railway mobile communication system based on “Long Term Evolution” (LTE), describes its network architecture, and especially analyzes the technical advantages and application value of the system in the high-speed railway wireless communication comparing with the existing GSM-R system. It also discusses feasibility of the GSM-R system's evolution to this high-speed railway mobile communication system and proposes the possible evolution model.
{"title":"A high-speed railway mobile communication system based on LTE","authors":"Gao Tingting, Sun Bin","doi":"10.1109/ICEIE.2010.5559665","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559665","url":null,"abstract":"Along with the developments of the high-speed railway, higher and higher technical requirements for the high-speed railway mobile communication system are raised. Since the “Global System for Mobile Communications Railways” (GSM-R) implemented today is based on GSM, the new technology in GSM evolution can be used in the highspeed railway mobile communication system to adapt to the new requirements. This paper introduces a high-speed railway mobile communication system based on “Long Term Evolution” (LTE), describes its network architecture, and especially analyzes the technical advantages and application value of the system in the high-speed railway wireless communication comparing with the existing GSM-R system. It also discusses feasibility of the GSM-R system's evolution to this high-speed railway mobile communication system and proposes the possible evolution model.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117126877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559834
Jui-Yu Wu
Optimization problems of a back-propagation neural network (BPNN) can be categorized into optimal network topology (including the number of neurons in a hidden layer, learning rate and the momentum term) and weights. This study focuses on the optimization of weights. The conventional BPNN uses the steepest descent method, i.e. a local optimization technique, to minimize an energy function (cost function) to find the BPNN weights. Therefore, a conventional BPNN cannot obtain global weights. An advanced simulated annealing (ASA) algorithm is a stochastic global method applied for solving a multi-dimensional objective function with boundary conditions. To overcome the drawback associated with the standard BPNN, this study attempts to optimize the weights of the BPNN using an ASA algorithm. Performance of the proposed ASA-based BPNN (named ASA-BPNN) is evaluated using a benchmark chaotic time series problem, i.e. the Mackey-Glass time series problem. Furthermore, the comparing experimental results for the ASA-BPNN with those of a standard BPNN reveals that training and generalization accuracies of the ASA-BPNN are superior to those of the standard BPNN for the test case.
{"title":"Advanced simulated annealing-based BPNN for forecasting chaotic time series","authors":"Jui-Yu Wu","doi":"10.1109/ICEIE.2010.5559834","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559834","url":null,"abstract":"Optimization problems of a back-propagation neural network (BPNN) can be categorized into optimal network topology (including the number of neurons in a hidden layer, learning rate and the momentum term) and weights. This study focuses on the optimization of weights. The conventional BPNN uses the steepest descent method, i.e. a local optimization technique, to minimize an energy function (cost function) to find the BPNN weights. Therefore, a conventional BPNN cannot obtain global weights. An advanced simulated annealing (ASA) algorithm is a stochastic global method applied for solving a multi-dimensional objective function with boundary conditions. To overcome the drawback associated with the standard BPNN, this study attempts to optimize the weights of the BPNN using an ASA algorithm. Performance of the proposed ASA-based BPNN (named ASA-BPNN) is evaluated using a benchmark chaotic time series problem, i.e. the Mackey-Glass time series problem. Furthermore, the comparing experimental results for the ASA-BPNN with those of a standard BPNN reveals that training and generalization accuracies of the ASA-BPNN are superior to those of the standard BPNN for the test case.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117178971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559805
T. Medeni, Ugurcan Kutluoglu, Asim Balci, Y. Kahramaner
This paper presents the initial results of a survey conducted in Turkey that aims to measure the effectiveness of the E-Government Gateway and satisfaction of citizens from the usage of the gateway system. Data has been collected from 1.500 qualitative responses to an open-ended question that requests (if there is) any other additional comment at the end of a quantitative survey. Collected data is categorized and analyzed with respect to subjective and practical criteria by the developers and operators of the gateway. Based on a maturity model classification for e-Government services from literature, selected examples of specific services are also provided. While the initial results reflect a positive perception of citizen users for the system, various suggestions and requests useful for development and improvement are especially noteworthy. For instance, citizen demand for more personalized information and service provision can be underlined. Findings from these initial survey outcomes are hoped to be not only incorporated into the e-Government service development in Turkey, but considered as useful for other ongoing practical and academic works on e-Government and ICT system evaluation in general, as well.
{"title":"Initial analysis and evaluation of citizen usage of E-Government Gateway in Turkey","authors":"T. Medeni, Ugurcan Kutluoglu, Asim Balci, Y. Kahramaner","doi":"10.1109/ICEIE.2010.5559805","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559805","url":null,"abstract":"This paper presents the initial results of a survey conducted in Turkey that aims to measure the effectiveness of the E-Government Gateway and satisfaction of citizens from the usage of the gateway system. Data has been collected from 1.500 qualitative responses to an open-ended question that requests (if there is) any other additional comment at the end of a quantitative survey. Collected data is categorized and analyzed with respect to subjective and practical criteria by the developers and operators of the gateway. Based on a maturity model classification for e-Government services from literature, selected examples of specific services are also provided. While the initial results reflect a positive perception of citizen users for the system, various suggestions and requests useful for development and improvement are especially noteworthy. For instance, citizen demand for more personalized information and service provision can be underlined. Findings from these initial survey outcomes are hoped to be not only incorporated into the e-Government service development in Turkey, but considered as useful for other ongoing practical and academic works on e-Government and ICT system evaluation in general, as well.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559909
I-Chyn Wey, Chun-Chien Wang
In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.
{"title":"Low-error and area-efficient fixed-width multiplier by using minor input correction vector","authors":"I-Chyn Wey, Chun-Chien Wang","doi":"10.1109/ICEIE.2010.5559909","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559909","url":null,"abstract":"In this paper, we propose a new error compensation circuit by using dual group minor input correction vector to lower compensation error. By utilizing the symmetric property of MIC and construct the error compensation circuit mainly by the “outer” partial products, the hardware complexity can be lowered and only increases slightly as the multiplier input bits increase. In the proposed 16-bit fixed-width multiplier, the truncation error can be reduced by 87% as compared with the direct-truncated multiplier and the transistor counts can be reduced by 47% as compared with the full-length multiplier.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559748
Huan Liu, Guangjun Li, Bo Yan, Qiang Li
Digital Down Converter is one of the key technologies in Software Defined Radio. In Digital Down Converter how to realize a high-speed, high-order FIR filter is an interesting problem. This paper proposes a modified Distributed Arithmetic, in which speed is improved and memory is saved compared with the traditional Distributed Arithmetic. The presented FIR filter based on the modified Distributed Arithmetic has been implemented in the form of ASIC which was fabricated in a SMIC 0.13µm CMOS process. The chip's sample rate can reach 10MSPS in the 80MHz system clock.
{"title":"A 100MHz Digital Down Converter with modified FIR filter for wideband software-defined radios","authors":"Huan Liu, Guangjun Li, Bo Yan, Qiang Li","doi":"10.1109/ICEIE.2010.5559748","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559748","url":null,"abstract":"Digital Down Converter is one of the key technologies in Software Defined Radio. In Digital Down Converter how to realize a high-speed, high-order FIR filter is an interesting problem. This paper proposes a modified Distributed Arithmetic, in which speed is improved and memory is saved compared with the traditional Distributed Arithmetic. The presented FIR filter based on the modified Distributed Arithmetic has been implemented in the form of ASIC which was fabricated in a SMIC 0.13µm CMOS process. The chip's sample rate can reach 10MSPS in the 80MHz system clock.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125918373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559745
M. A. I. Fakharaldien, Siti Normazial Ihsan, Jasni Mohamad Zain
In this paper we present a middleware for storing and retrieving XML document in relational databases. To store XML documents in relational databases, several mapping prototypes can be used. In this prototype we chose XParent model mapping method and free of cost available technologies MySQL, Php MyAdmin and PHP classes are used the example. The key to middleware prototype is storing and retrieving XML document in a relational database, providing a user interface for XML manipulation, independent of proprietorship and without doing any modification in its basic structure. As the proposed prototype is using XParent so it will be proved to be an efficient solution with respect to query processing specially recursive XML queries and updating. The middleware prototype can also be used as the benchmarking tool for the researchers to compare various schema-oblivious XML mapping strategies after adding them as new collection.
{"title":"A middleware prototype for storing and quering XML documents in RDB using XParent model mapping schema","authors":"M. A. I. Fakharaldien, Siti Normazial Ihsan, Jasni Mohamad Zain","doi":"10.1109/ICEIE.2010.5559745","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559745","url":null,"abstract":"In this paper we present a middleware for storing and retrieving XML document in relational databases. To store XML documents in relational databases, several mapping prototypes can be used. In this prototype we chose XParent model mapping method and free of cost available technologies MySQL, Php MyAdmin and PHP classes are used the example. The key to middleware prototype is storing and retrieving XML document in a relational database, providing a user interface for XML manipulation, independent of proprietorship and without doing any modification in its basic structure. As the proposed prototype is using XParent so it will be proved to be an efficient solution with respect to query processing specially recursive XML queries and updating. The middleware prototype can also be used as the benchmarking tool for the researchers to compare various schema-oblivious XML mapping strategies after adding them as new collection.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123696700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559870
Wonki Park, Sungmin Lee
This paper presents a low-power CMOS multichannel transmitter that achieves a data rate of 3.125Gb/s/ch. The LVDS (Low-voltage differential-signaling) driver is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. The prototype chip is comprised of 4 channels and was fabricated in a 0.18 μm standard CMOS process. The measured output jitter of transmitter is 100ps, peak-to-peak(0.31UI). The area of the chip is 0.045 mm2 and the power consumption is about 48mW/ch.
{"title":"Design of LVDS driver based CMOS transmitter for a high speed serial link","authors":"Wonki Park, Sungmin Lee","doi":"10.1109/ICEIE.2010.5559870","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559870","url":null,"abstract":"This paper presents a low-power CMOS multichannel transmitter that achieves a data rate of 3.125Gb/s/ch. The LVDS (Low-voltage differential-signaling) driver is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. The prototype chip is comprised of 4 channels and was fabricated in a 0.18 μm standard CMOS process. The measured output jitter of transmitter is 100ps, peak-to-peak(0.31UI). The area of the chip is 0.045 mm2 and the power consumption is about 48mW/ch.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125575611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559884
Vahab Choubine, Mohamad Javad Rostami, A. Mazandarani
Wireless sensor network with mobile sink is currently under study. In this paper, we propose a novel sink mobility problem called OSM in these networks. Then we present a solution called PSSM to this problem. According to PSSM, sinks dynamically move toward traffic sources in a way to reduce average hop count. Our simulation experiments show that applying PSSM to the LURP routing protocol effectively reduces average packet delay, average hop count, and energy consumption in comparison with the original LURP.
{"title":"Path-shrinking sink mobility in wireless sensor networks","authors":"Vahab Choubine, Mohamad Javad Rostami, A. Mazandarani","doi":"10.1109/ICEIE.2010.5559884","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559884","url":null,"abstract":"Wireless sensor network with mobile sink is currently under study. In this paper, we propose a novel sink mobility problem called OSM in these networks. Then we present a solution called PSSM to this problem. According to PSSM, sinks dynamically move toward traffic sources in a way to reduce average hop count. Our simulation experiments show that applying PSSM to the LURP routing protocol effectively reduces average packet delay, average hop count, and energy consumption in comparison with the original LURP.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115208347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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