Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559725
Lili Diao, Chengzhong Yang
In internet era, though emails turn into one of the most popular way for communication, spam emails also bother people seriously. As a result, research on email filtering has become a hot topic with much effort put into this area. Unfortunately, in the real-world application, the large-scale training email dataset which differs from the assumption made in experiment challenges both efficiency and effectiveness. Thus, a new promising method to filter emails is in need. In this paper, we propose an SVM based machine learning method to compress the training set with minimal information loss. The key process is that we reduce large-scale training email set according to the distribution of Support Vectors produced by SVM training. Then a compressed training set is obtained and makes a great contribution to saving time and keeping precision in generating anti-spam models. Experiments show that trained anti-spam classifier can get a better performance by applying our compressing approach.
{"title":"Training anti-spam models with smaller training set via SVM way","authors":"Lili Diao, Chengzhong Yang","doi":"10.1109/ICEIE.2010.5559725","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559725","url":null,"abstract":"In internet era, though emails turn into one of the most popular way for communication, spam emails also bother people seriously. As a result, research on email filtering has become a hot topic with much effort put into this area. Unfortunately, in the real-world application, the large-scale training email dataset which differs from the assumption made in experiment challenges both efficiency and effectiveness. Thus, a new promising method to filter emails is in need. In this paper, we propose an SVM based machine learning method to compress the training set with minimal information loss. The key process is that we reduce large-scale training email set according to the distribution of Support Vectors produced by SVM training. Then a compressed training set is obtained and makes a great contribution to saving time and keeping precision in generating anti-spam models. Experiments show that trained anti-spam classifier can get a better performance by applying our compressing approach.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128389083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559782
Tang Huai-zhi, Wu Kening, Tang Min
Land-use regionalization is an important means to implement land use control, and it is significant for establishing land-use direction scientifically, setting reasonable land use structure, improving land use intensification, and promoting the coordinated development of regional. Regional function division of land use is a new spatial-division of land use, which is proposed in the third round of the overall land use planning in China, in that the traditional partition method cannot fully meet the planning needs of the new situation. This paper proposes a compilation method for regional function division of land use, combined with land-use strategy, and uses of SWOT, GIS and land use conflict analysis methods, carried out empirical research on regional function division of land use in Taiyuan city qualitatively and quantitatively.
{"title":"Research on regional function division of land use in Taiyuan city","authors":"Tang Huai-zhi, Wu Kening, Tang Min","doi":"10.1109/ICEIE.2010.5559782","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559782","url":null,"abstract":"Land-use regionalization is an important means to implement land use control, and it is significant for establishing land-use direction scientifically, setting reasonable land use structure, improving land use intensification, and promoting the coordinated development of regional. Regional function division of land use is a new spatial-division of land use, which is proposed in the third round of the overall land use planning in China, in that the traditional partition method cannot fully meet the planning needs of the new situation. This paper proposes a compilation method for regional function division of land use, combined with land-use strategy, and uses of SWOT, GIS and land use conflict analysis methods, carried out empirical research on regional function division of land use in Taiyuan city qualitatively and quantitatively.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133807997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559682
Surafel Teshome, Tae-Sun Chung
Flash memory database systems are relatively new area of research interest in computing community. Most database techniques, already developed and proposed, are based on the assumption that the database is hard disk resident, due to this fact the cost measurement of query algorithms is highly dependent on the mechanical nature of hard disks. But the read, write, erase behavior of flash memories are radically different from hard disks, so that new measures of query costs that are tuned by the characteristics of flash memories should be introduced. In this paper we propose a new query cost measurement procedure for read intensive queries like join. We then compare and contrast already developed join algorithms with the new cost measurement.
{"title":"Query cost estimation for read intensive flash memory based database systems","authors":"Surafel Teshome, Tae-Sun Chung","doi":"10.1109/ICEIE.2010.5559682","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559682","url":null,"abstract":"Flash memory database systems are relatively new area of research interest in computing community. Most database techniques, already developed and proposed, are based on the assumption that the database is hard disk resident, due to this fact the cost measurement of query algorithms is highly dependent on the mechanical nature of hard disks. But the read, write, erase behavior of flash memories are radically different from hard disks, so that new measures of query costs that are tuned by the characteristics of flash memories should be introduced. In this paper we propose a new query cost measurement procedure for read intensive queries like join. We then compare and contrast already developed join algorithms with the new cost measurement.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129603915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559755
Sapna, Manju Sharma
This paper presents the WAN performance in low load campus network with & without Load Balancer. In this network model, generic LANs models are used and impact of increased FTP load on the network performance are investigated. In this paper, a simulated environment is created where many applications are in use at a time and their mutual effects thereof. This network model is based on OPNET IT GURU Academic Edition. This OPNET is used to develop a new model suitable for Campus/University environment. This model is tested against various types of applications (FTP, ATM, Remote Login, and Print) in 5 LANs and found that among a set of parameters with and without Load balancer, Firewall and IP cloud. This OPNET simulation showed the impact of load balancing on WAN for different types of applications.
本文介绍了在低负载校园网中使用和不使用负载均衡器时广域网的性能。在该网络模型中，使用了通用局域网模型，并研究了FTP负载增加对网络性能的影响。在本文中，创建了一个模拟环境，其中同时使用许多应用程序及其相互影响。该网络模型基于OPNET IT GURU学术版。利用OPNET开发了一个适合校园/大学环境的新模型。该模型在5个局域网中针对各种类型的应用程序(FTP、ATM、远程登录和打印)进行了测试，发现在一组参数中，有和没有负载平衡器、防火墙和IP云。这个OPNET模拟显示了负载平衡对不同类型应用程序在广域网上的影响。
{"title":"Performance evaluation of a wired network with & without Load Balancer and Firewall","authors":"Sapna, Manju Sharma","doi":"10.1109/ICEIE.2010.5559755","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559755","url":null,"abstract":"This paper presents the WAN performance in low load campus network with & without Load Balancer. In this network model, generic LANs models are used and impact of increased FTP load on the network performance are investigated. In this paper, a simulated environment is created where many applications are in use at a time and their mutual effects thereof. This network model is based on OPNET IT GURU Academic Edition. This OPNET is used to develop a new model suitable for Campus/University environment. This model is tested against various types of applications (FTP, ATM, Remote Login, and Print) in 5 LANs and found that among a set of parameters with and without Load balancer, Firewall and IP cloud. This OPNET simulation showed the impact of load balancing on WAN for different types of applications.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134555881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559844
Satyanand Namana, S. Baishya, K. Koley
An analytical sub-threshold surface potential model for double gate MOSFET (DG-MOSFET) is presented incorporating the edge effects at the source and drain ends. As the gate length of DG MOSFETs is scaled down, the barrier lowering becomes very important. A fitting parameter α is introduced to compensate this effect. The results obtained with this modeled equation are well matched with the results from 2-D numerical simulator TCAD.
{"title":"A subthreshold surface potential modeling of drain/source edge effect on double gate MOS transistor","authors":"Satyanand Namana, S. Baishya, K. Koley","doi":"10.1109/ICEIE.2010.5559844","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559844","url":null,"abstract":"An analytical sub-threshold surface potential model for double gate MOSFET (DG-MOSFET) is presented incorporating the edge effects at the source and drain ends. As the gate length of DG MOSFETs is scaled down, the barrier lowering becomes very important. A fitting parameter α is introduced to compensate this effect. The results obtained with this modeled equation are well matched with the results from 2-D numerical simulator TCAD.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134577732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559771
M. Sharkas, Amr M. El-Helw, E. AlSaba
Face detection plays an important role in many applications such as video surveillance, face recognition, face image database management etc. This paper presents a new technique which reduces the learning and detection time using the multi block local binary pattern (MBLBP) with Multi-exit Asymmetric Boosting. In this technique, the selected features are reduced by around 1/20 of Haar-like method so the learning time is also reduced by about 1/20. The detection time is also reduced by more than 1/4 of Haar-like detector. Multi-exit Asymmetric Boosting reduces features by about 1/5 of the cascade method so the learning and detection time is also reduced.
{"title":"MBLBP face detection with multi-exit Asymmetric Boosting","authors":"M. Sharkas, Amr M. El-Helw, E. AlSaba","doi":"10.1109/ICEIE.2010.5559771","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559771","url":null,"abstract":"Face detection plays an important role in many applications such as video surveillance, face recognition, face image database management etc. This paper presents a new technique which reduces the learning and detection time using the multi block local binary pattern (MBLBP) with Multi-exit Asymmetric Boosting. In this technique, the selected features are reduced by around 1/20 of Haar-like method so the learning time is also reduced by about 1/20. The detection time is also reduced by more than 1/4 of Haar-like detector. Multi-exit Asymmetric Boosting reduces features by about 1/5 of the cascade method so the learning and detection time is also reduced.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133342225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559715
V. Agarwal, Pansoo Kim, D. Oh, D. Ahn
Computational complexity of a coherent correlator is dominated by the number of complex multiplications and additions involved in process. In this paper a unique multiplier-less approach of coherent correlation has been proposed for Digital Video Broadcasting Second Generation (DVB-S2) receiver. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving as well as it improves the processing speed of the correlator over the conventional approach. It is also advantageous in terms of On-chip memory requirement. The functionality of the design has been verified through simulation and synthesis of the existing and proposed correlation scheme. The proposed architecture is optimized in terms of area with 97% reduction in number of LUTs. The critical speed of design on Virtex4 FPGA is 1364 MHz and it consumes 1.29W power which is 9.28% of the power consumed by conventional architectures. The proposed coherent correlator architecture can be used with the Data Aided (DA) receiver schemes (such as Frame synchronization, SNR estimation) used in the DVB-S2 standard.
{"title":"Computationally efficient coherent correlator design for DVB-S2 receiver","authors":"V. Agarwal, Pansoo Kim, D. Oh, D. Ahn","doi":"10.1109/ICEIE.2010.5559715","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559715","url":null,"abstract":"Computational complexity of a coherent correlator is dominated by the number of complex multiplications and additions involved in process. In this paper a unique multiplier-less approach of coherent correlation has been proposed for Digital Video Broadcasting Second Generation (DVB-S2) receiver. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving as well as it improves the processing speed of the correlator over the conventional approach. It is also advantageous in terms of On-chip memory requirement. The functionality of the design has been verified through simulation and synthesis of the existing and proposed correlation scheme. The proposed architecture is optimized in terms of area with 97% reduction in number of LUTs. The critical speed of design on Virtex4 FPGA is 1364 MHz and it consumes 1.29W power which is 9.28% of the power consumed by conventional architectures. The proposed coherent correlator architecture can be used with the Data Aided (DA) receiver schemes (such as Frame synchronization, SNR estimation) used in the DVB-S2 standard.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129373774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559684
Young Jin Lee, S. K. S. Lee, S. H. Kim, H. S. Jeong, S. Hong, D. Han, G. Han
Recently intermodal transportation systems are significantly considered as enhanced technique or future railroad Logistics. These are aimed for particularly reducing complicated job process in the railroad based transportation and relevant logistic cost in economic viewpoint. In this paper we suggest a horizontal transfer system using hydro-motor and hydro-cylinder for intermodal transportation system. This system can assist to transfer the containers horizontally for train logistics automations.
{"title":"A development of horizontal transfer robot for horizontal loading/unloading of container","authors":"Young Jin Lee, S. K. S. Lee, S. H. Kim, H. S. Jeong, S. Hong, D. Han, G. Han","doi":"10.1109/ICEIE.2010.5559684","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559684","url":null,"abstract":"Recently intermodal transportation systems are significantly considered as enhanced technique or future railroad Logistics. These are aimed for particularly reducing complicated job process in the railroad based transportation and relevant logistic cost in economic viewpoint. In this paper we suggest a horizontal transfer system using hydro-motor and hydro-cylinder for intermodal transportation system. This system can assist to transfer the containers horizontally for train logistics automations.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559797
Maryam Sabzevari, S. Toosizadeh, S. R. Quchani, Vahid Abrishami
For a given animated avatar or face, synthesizing facial expressions in a fast and accurate way is a challenging problem. This paper presents a multi-cue methodology in order to generate facial expressions in a real time manner. The proposed approach first extracts the graph of the face using constrained local model (CLM) and generates a shape based feature vector. Secondly, it employs this feature vector to train a 3 layer deep belief network. After training, the deep belief network has the ability to generate the shape of an ideal facial expression for an input face graph. A post processing step then is applied to produce proper wrinkles and illumination changes which are related to that special facial expression. Employing a small feature vector, instead of a vector which includes all pixels of the face image, increases the speed of both training and generation phase for a deep belief network and makes it intrinsically suitable for real-time purposes. In addition, this approach is independent from the format of the input image and can be used for various types of images, including color images. The experimental results demonstrate the accuracy of our algorithm.
对于给定的动画角色或面部，快速准确地合成面部表情是一个具有挑战性的问题。本文提出了一种实时生成面部表情的多线索方法。该方法首先利用约束局部模型(constrained local model, CLM)提取人脸图形，生成基于形状的特征向量;其次，利用该特征向量训练3层深度信念网络;经过训练，深度信念网络具有为输入的人脸图生成理想面部表情形状的能力。然后应用后处理步骤来产生与特殊面部表情相关的适当皱纹和照明变化。采用小的特征向量，而不是包含人脸图像所有像素的向量，提高了深度信念网络的训练和生成阶段的速度，使其本质上适合于实时目的。此外，这种方法与输入图像的格式无关，可用于各种类型的图像，包括彩色图像。实验结果证明了算法的准确性。
{"title":"A fast and accurate facial expression synthesis system for color face images using face graph and deep belief network","authors":"Maryam Sabzevari, S. Toosizadeh, S. R. Quchani, Vahid Abrishami","doi":"10.1109/ICEIE.2010.5559797","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559797","url":null,"abstract":"For a given animated avatar or face, synthesizing facial expressions in a fast and accurate way is a challenging problem. This paper presents a multi-cue methodology in order to generate facial expressions in a real time manner. The proposed approach first extracts the graph of the face using constrained local model (CLM) and generates a shape based feature vector. Secondly, it employs this feature vector to train a 3 layer deep belief network. After training, the deep belief network has the ability to generate the shape of an ideal facial expression for an input face graph. A post processing step then is applied to produce proper wrinkles and illumination changes which are related to that special facial expression. Employing a small feature vector, instead of a vector which includes all pixels of the face image, increases the speed of both training and generation phase for a deep belief network and makes it intrinsically suitable for real-time purposes. In addition, this approach is independent from the format of the input image and can be used for various types of images, including color images. The experimental results demonstrate the accuracy of our algorithm.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121798728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-02DOI: 10.1109/ICEIE.2010.5559741
Mohammad Nourian Awal Noughabi, B. Sadeghiyan
In this paper, we present a framework for the design of S-boxes used in ciphers based on neural networks. It can yield S-boxes with different input and output length. The designed n × n S-boxes satisfy the desired cryptographic properties of non-linearity, completeness, strict avalanche, and output bits independence criteria. We propose a four layer topology, where the number of neurons, located at the input layer, is two times the number of input bits of the designed S-box and also, the number of neurons, located at the first hidden layer, is as equal as input layer neurons, while its second hidden layer included n/2 neurons, and its output layer included n neurons. The input value of the designed S-boxes consists of n-bit input vector and constant n-bit initial value (IV). We apply a Sigmoid nonlinear function as the activation function of our scheme. The values of weights were obtained through error back propagation learning algorithm, while a training set is used for learning. The used training set consists some different pairs of plaintexts and ciphertexts with AES's S-box. We also implement an 8 × 8 S-box based on neural networks with the essential security criteria. The results indicate that the proposed scheme can yield S-boxes with the desired cryptographic properties.
本文提出了一种基于神经网络的s盒密码设计框架。可生产不同输入输出长度的s盒。所设计的n × n s盒满足非线性、完备性、严格的雪崩和输出位无关标准的要求。我们提出了一个四层拓扑，其中位于输入层的神经元数量是设计的S-box输入位数量的两倍，并且位于第一隐藏层的神经元数量与输入层神经元数量相等，而其第二层隐藏层包含n/2个神经元，其输出层包含n个神经元。设计的s盒的输入值由n位输入向量和恒定n位初始值(IV)组成。我们采用Sigmoid非线性函数作为我们方案的激活函数。通过误差反向传播学习算法获得权值，并使用训练集进行学习。使用的训练集由若干对不同的明文和密文组成，并带有AES的S-box。我们还实现了一个基于神经网络的8 × 8 S-box，具有基本的安全标准。结果表明，该方案能够产生具有理想密码特性的s盒。
{"title":"Design of S-boxes based on neural networks*","authors":"Mohammad Nourian Awal Noughabi, B. Sadeghiyan","doi":"10.1109/ICEIE.2010.5559741","DOIUrl":"https://doi.org/10.1109/ICEIE.2010.5559741","url":null,"abstract":"In this paper, we present a framework for the design of S-boxes used in ciphers based on neural networks. It can yield S-boxes with different input and output length. The designed n × n S-boxes satisfy the desired cryptographic properties of non-linearity, completeness, strict avalanche, and output bits independence criteria. We propose a four layer topology, where the number of neurons, located at the input layer, is two times the number of input bits of the designed S-box and also, the number of neurons, located at the first hidden layer, is as equal as input layer neurons, while its second hidden layer included n/2 neurons, and its output layer included n neurons. The input value of the designed S-boxes consists of n-bit input vector and constant n-bit initial value (IV). We apply a Sigmoid nonlinear function as the activation function of our scheme. The values of weights were obtained through error back propagation learning algorithm, while a training set is used for learning. The used training set consists some different pairs of plaintexts and ciphertexts with AES's S-box. We also implement an 8 × 8 S-box based on neural networks with the essential security criteria. The results indicate that the proposed scheme can yield S-boxes with the desired cryptographic properties.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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