Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173963
Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen
Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.
{"title":"High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis","authors":"Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen","doi":"10.1109/ETS56758.2023.10173963","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173963","url":null,"abstract":"Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128393572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174077
Theofilos Spyrou, H. Stratigopoulos
We propose an on-line testing methodology for neuromorphic hardware supporting spiking neural networks. Testing aims at detecting in real-time abnormal operation due to hardware-level faults, as well as screening of outlier or corner inputs that are prone to misprediction. Testing is enabled by two on-chip classifiers that prognosticate, based on a low-dimensional set of features extracted with spike counting, whether the network will make a correct prediction. The system of classifiers is capable of evaluating the confidence of the decision, and when the confidence is judged low a replay operation helps to resolve the ambiguity. The testing methodology is demonstrated by fully embedding it in a custom FPGA-based neuromorphic hardware platform. It operates in the background being totally non-intrusive to the network operation, while offering a zero-latency test decision for the vast majority of inferences.
{"title":"On-Line Testing of Neuromorphic Hardware","authors":"Theofilos Spyrou, H. Stratigopoulos","doi":"10.1109/ETS56758.2023.10174077","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174077","url":null,"abstract":"We propose an on-line testing methodology for neuromorphic hardware supporting spiking neural networks. Testing aims at detecting in real-time abnormal operation due to hardware-level faults, as well as screening of outlier or corner inputs that are prone to misprediction. Testing is enabled by two on-chip classifiers that prognosticate, based on a low-dimensional set of features extracted with spike counting, whether the network will make a correct prediction. The system of classifiers is capable of evaluating the confidence of the decision, and when the confidence is judged low a replay operation helps to resolve the ambiguity. The testing methodology is demonstrated by fully embedding it in a custom FPGA-based neuromorphic hardware platform. It operates in the background being totally non-intrusive to the network operation, while offering a zero-latency test decision for the vast majority of inferences.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128495226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173981
B. Sapui, Jonas Krautter, M. Mayahinia, A. Jafari, Dennis R. E. Gnad, Sergej Meschkov, M. Tahoori
To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.
{"title":"Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies","authors":"B. Sapui, Jonas Krautter, M. Mayahinia, A. Jafari, Dennis R. E. Gnad, Sergej Meschkov, M. Tahoori","doi":"10.1109/ETS56758.2023.10173981","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173981","url":null,"abstract":"To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174178
Marcello Traiola, A. Kritikakou, O. Sentieys
Deep Neural Networks (DNNs) show promising performance in several application domains, such as robotics, aerospace, smart healthcare, and autonomous driving. Nevertheless, DNN results may be incorrect, not only because of the network intrinsic inaccuracy, but also due to faults affecting the hardware. Indeed, hardware faults may impact the DNN inference process and lead to prediction failures. Therefore, ensuring the fault tolerance of DNN is crucial. However, common fault tolerance approaches are not cost-effective for DNNs protection, because of the prohibitive overheads due to the large size of DNNs and of the required memory for parameter storage. In this work, we propose a comprehensive framework to assess the fault tolerance of DNNs and cost-effectively protect them. As a first step, the proposed framework performs data-type-and-layer-based fault injection, driven by the DNN characteristics. As a second step, it uses classification-based machine learning methods in order to predict the criticality, not only of network parameters, but also of their bits. Last, dedicated Error Correction Codes (ECCs) are selectively inserted to protect the critical parameters and bits, hence protecting the DNNs with low cost. Thanks to the proposed framework, we explored and protected two Convolutional Neural Networks (CNNs), each with four different data encoding. The results show that it is possible to protect the critical network parameters with selective ECCs while saving up to 83% memory w.r.t. conventional ECC approaches.
{"title":"harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs","authors":"Marcello Traiola, A. Kritikakou, O. Sentieys","doi":"10.1109/ETS56758.2023.10174178","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174178","url":null,"abstract":"Deep Neural Networks (DNNs) show promising performance in several application domains, such as robotics, aerospace, smart healthcare, and autonomous driving. Nevertheless, DNN results may be incorrect, not only because of the network intrinsic inaccuracy, but also due to faults affecting the hardware. Indeed, hardware faults may impact the DNN inference process and lead to prediction failures. Therefore, ensuring the fault tolerance of DNN is crucial. However, common fault tolerance approaches are not cost-effective for DNNs protection, because of the prohibitive overheads due to the large size of DNNs and of the required memory for parameter storage. In this work, we propose a comprehensive framework to assess the fault tolerance of DNNs and cost-effectively protect them. As a first step, the proposed framework performs data-type-and-layer-based fault injection, driven by the DNN characteristics. As a second step, it uses classification-based machine learning methods in order to predict the criticality, not only of network parameters, but also of their bits. Last, dedicated Error Correction Codes (ECCs) are selectively inserted to protect the critical parameters and bits, hence protecting the DNNs with low cost. Thanks to the proposed framework, we explored and protected two Convolutional Neural Networks (CNNs), each with four different data encoding. The results show that it is possible to protect the critical network parameters with selective ECCs while saving up to 83% memory w.r.t. conventional ECC approaches.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128894958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174071
{"title":"Half Title Page","authors":"","doi":"10.1109/ets56758.2023.10174071","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174071","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174076
Bruno E. Forlin, Wouter van Huffelen, C. Cazzaniga, P. Rech, Nikolaos S. Alachiotis, M. Ottavi
Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct functioning, they must be capable of withstanding failures without sacrificing much performance. When adjusting a soft core for these applications, it is essential to know where redundancies are necessary, to avoid unnecessary overhead. We characterize the reliability of an unprotected RISC-V microcontroller using an accelerated neutron beam. Our investigation shows that, for our chosen benchmark and processor, the user data in the memory banks is the leading cause of the total number of errors in the application. By reversing the benchmark operations, we could root cause the origin of the observed errors and found that most of the data corruption detected during the runs stem from previously corrupt input data or from output data that were corrupted while transmitting.
{"title":"An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?","authors":"Bruno E. Forlin, Wouter van Huffelen, C. Cazzaniga, P. Rech, Nikolaos S. Alachiotis, M. Ottavi","doi":"10.1109/ETS56758.2023.10174076","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174076","url":null,"abstract":"Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct functioning, they must be capable of withstanding failures without sacrificing much performance. When adjusting a soft core for these applications, it is essential to know where redundancies are necessary, to avoid unnecessary overhead. We characterize the reliability of an unprotected RISC-V microcontroller using an accelerated neutron beam. Our investigation shows that, for our chosen benchmark and processor, the user data in the memory banks is the leading cause of the total number of errors in the application. By reversing the benchmark operations, we could root cause the origin of the observed errors and found that most of the data corruption detected during the runs stem from previously corrupt input data or from output data that were corrupted while transmitting.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131960728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174135
Shao-Chun Hung, Arjun Chaudhuri, K. Chakrabarty
Monolithic 3D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this paper, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.
{"title":"Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*","authors":"Shao-Chun Hung, Arjun Chaudhuri, K. Chakrabarty","doi":"10.1109/ETS56758.2023.10174135","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174135","url":null,"abstract":"Monolithic 3D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this paper, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Neuromorphic computation is based on spike trains in which the location and frequency of spikes occurring within the network guide the execution. This paper develops a frame-work to monitor the correctness of a neuromorphic program’s execution using model-based redundancy in which a software-based monitor compares discrepancies between the behavior of neurons mapped to hardware and that predicted by a corresponding mathematical model in real time. Our approach reduces the hardware overhead needed to support the monitoring infrastructure and minimizes intrusion on the executing application. Fault-injection experiments utilizing CARLSim, a high-fidelity SNN simulator, show that the framework achieves high fault coverage using parsimonious models which can operate with low computational overhead in real time.
{"title":"Online Performance Monitoring of Neuromorphic Computing Systems","authors":"Abhishek Kumar Mishra, Anup Das, Nagarajan Kandasamy","doi":"10.1109/ETS56758.2023.10173860","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173860","url":null,"abstract":"Neuromorphic computation is based on spike trains in which the location and frequency of spikes occurring within the network guide the execution. This paper develops a frame-work to monitor the correctness of a neuromorphic program’s execution using model-based redundancy in which a software-based monitor compares discrepancies between the behavior of neurons mapped to hardware and that predicted by a corresponding mathematical model in real time. Our approach reduces the hardware overhead needed to support the monitoring infrastructure and minimizes intrusion on the executing application. Fault-injection experiments utilizing CARLSim, a high-fidelity SNN simulator, show that the framework achieves high fault coverage using parsimonious models which can operate with low computational overhead in real time.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174156
Tobias Faller, N. I. Deligiannis, Markus Schwörer, M. Reorda, B. Becker
Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. The creation of such SBST programs often requires time-consuming manual labour that is expensive and requires in-depth knowledge of the processor’s architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST. Constraints for the BMC problem are encoded in a circuit called Validity Checker Module (VCM) and applied during SBST generation.In this paper, we focus on presenting a VCM architecture and a constraint set that allows building SBSTs that make minimal assumptions about the firmware, targeting hard-to-test faults in the ALU and register file of multiple scalar, in-order RISC-V processor families. The VCM architecture consists of a processor-specific mapping layer and a generic constraint set connected via a well-defined interface. The generic constraint set enforces the desired SBST behaviour, including controlling the processor’s pipeline state, memory accesses, and with that executed instructions, register state, and fault propagations. Using a generic constraint set allows for rapid SBST generation targeting new RISC-V processor families while keeping the generic constraints untouched. Lastly, we evaluate this approach on two RISC-V processor families, namely the DarkRISCV and a proprietary, industrial core showing the portability and strength of the approach, allowing for rapidly targeting new processors.
{"title":"Constraint-Based Automatic SBST Generation for RISC-V Processor Families","authors":"Tobias Faller, N. I. Deligiannis, Markus Schwörer, M. Reorda, B. Becker","doi":"10.1109/ETS56758.2023.10174156","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174156","url":null,"abstract":"Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. The creation of such SBST programs often requires time-consuming manual labour that is expensive and requires in-depth knowledge of the processor’s architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST. Constraints for the BMC problem are encoded in a circuit called Validity Checker Module (VCM) and applied during SBST generation.In this paper, we focus on presenting a VCM architecture and a constraint set that allows building SBSTs that make minimal assumptions about the firmware, targeting hard-to-test faults in the ALU and register file of multiple scalar, in-order RISC-V processor families. The VCM architecture consists of a processor-specific mapping layer and a generic constraint set connected via a well-defined interface. The generic constraint set enforces the desired SBST behaviour, including controlling the processor’s pipeline state, memory accesses, and with that executed instructions, register state, and fault propagations. Using a generic constraint set allows for rapid SBST generation targeting new RISC-V processor families while keeping the generic constraints untouched. Lastly, we evaluate this approach on two RISC-V processor families, namely the DarkRISCV and a proprietary, industrial core showing the portability and strength of the approach, allowing for rapidly targeting new processors.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174052
Upoma Das, Sazadur Rahman, N. Anandakumar, K. Z. Azar, Fahim Rahman, M. Tehranipoor, Farimah Farahmandi
With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips (SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that IP watermarking is a potential solution to the copyright protection of IP cores, this paper proposes PSC-Watermark as a power side-channel-based IP authentication methodology using clock gates. PSC-Watermark embeds a power signature with very minimal modification to the IP core. It is done by reusing the existing clock gates to modify the dynamic power consumption inside the IP (in an SoC) based on an applied challenge, and it generates a unique power trace that works as a signature of the IP. Our experimental results show that this power signature can be robustly/effectively verified, even with the interferences emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several benchmarks of varying size (i.e., MIPS, openMSP430, or1200) in the presence of multiple non-watermarked cores operating in parallel and obtain > 90% confidence rate in proving the ownership of each watermarked IP core. Furthermore, the IP cores are watermarked in a subtle and obfuscated way with < 4% overhead, which makes the proposed technique hard to detect, remove or modify.
{"title":"PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates","authors":"Upoma Das, Sazadur Rahman, N. Anandakumar, K. Z. Azar, Fahim Rahman, M. Tehranipoor, Farimah Farahmandi","doi":"10.1109/ETS56758.2023.10174052","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174052","url":null,"abstract":"With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips (SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that IP watermarking is a potential solution to the copyright protection of IP cores, this paper proposes PSC-Watermark as a power side-channel-based IP authentication methodology using clock gates. PSC-Watermark embeds a power signature with very minimal modification to the IP core. It is done by reusing the existing clock gates to modify the dynamic power consumption inside the IP (in an SoC) based on an applied challenge, and it generates a unique power trace that works as a signature of the IP. Our experimental results show that this power signature can be robustly/effectively verified, even with the interferences emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several benchmarks of varying size (i.e., MIPS, openMSP430, or1200) in the presence of multiple non-watermarked cores operating in parallel and obtain > 90% confidence rate in proving the ownership of each watermarked IP core. Furthermore, the IP cores are watermarked in a subtle and obfuscated way with < 4% overhead, which makes the proposed technique hard to detect, remove or modify.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127684710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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