Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10173956
{"title":"ETS23 Sponsors and Organizers","authors":"","doi":"10.1109/ets56758.2023.10173956","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10173956","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174024
G. Léger, A. Ginés, E. Peralías, Valentín Gutiérrez, C. Dominguez, M. A. Jalón, L. Carranza
One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.
{"title":"A Single-Event Latchup setup for high-precision AMS circuits","authors":"G. Léger, A. Ginés, E. Peralías, Valentín Gutiérrez, C. Dominguez, M. A. Jalón, L. Carranza","doi":"10.1109/ETS56758.2023.10174024","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174024","url":null,"abstract":"One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174063
Alper Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, S. Sezer, M. Ottavi, O. Ergin
Instruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC’s fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processing-in-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-to-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.
{"title":"DEV-PIM: Dynamic Execution Validation with Processing-in-Memory","authors":"Alper Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, S. Sezer, M. Ottavi, O. Ergin","doi":"10.1109/ETS56758.2023.10174063","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174063","url":null,"abstract":"Instruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC’s fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processing-in-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-to-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127432567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174113
M. Fieback, Filip Bradaric, M. Taouil, S. Hamdioui
Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.
{"title":"Online Fault Detection and Diagnosis in RRAM","authors":"M. Fieback, Filip Bradaric, M. Taouil, S. Hamdioui","doi":"10.1109/ETS56758.2023.10174113","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174113","url":null,"abstract":"Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174093
J. Rajski, Maciej Trawka, J. Tyszer, Bartosz Wlodarczak
Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.
{"title":"Hybrid Ring Generators for In-System Test Applications","authors":"J. Rajski, Maciej Trawka, J. Tyszer, Bartosz Wlodarczak","doi":"10.1109/ETS56758.2023.10174093","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174093","url":null,"abstract":"Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115546638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174110
J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda
1 Currently, Graphics Processing Units (GPUs) are extensively used in several safety-critical domains to support the implementation of complex operations where reliability is a major concern. Some internal cores, such as Special Function Units (SFUs), are increasingly adopted, being crucial to achieving the necessary performance in multimedia, scientific computing, and neural network training. Unfortunately, these cores are highly unexplored in terms of their impact on reliability.In this work, we evaluate the incidence of SFUs on the reliability of GPUs when affected by soft errors. First, we analyze the impact of SFU cores on the GPU’s reliability and the running workloads. We resort to applications configured to use or not the SFU cores and evaluate the effect of soft errors by using a software-based fault injection environment (NVBITFI) in an NVIDIA Ampere GPU. Then, we focus on evaluating the impact of soft errors arising in the SFUs. A fine-grain RTL evaluation determines the soft error effects on two SFUs architectures for GPUs (’fused’ and ’modular’). The experiments use an open-source GPU (FlexGripPlus) instrumented with both SFU architectures. The results suggest that workloads using SFUs are more vulnerable to faults (from 1 up to 5 orders of magnitude for the analyzed applications). Moreover, the RTL results show that modular SFUs are less vulnerable to faults (in up to 47% for the analyzed workloads) in comparison with fused SFUs (base of commercial devices), so allowing us to identify the more robust SFU architecture.
{"title":"Evaluating the Prevalence of SFUs in the Reliability of GPUs","authors":"J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda","doi":"10.1109/ETS56758.2023.10174110","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174110","url":null,"abstract":"1 Currently, Graphics Processing Units (GPUs) are extensively used in several safety-critical domains to support the implementation of complex operations where reliability is a major concern. Some internal cores, such as Special Function Units (SFUs), are increasingly adopted, being crucial to achieving the necessary performance in multimedia, scientific computing, and neural network training. Unfortunately, these cores are highly unexplored in terms of their impact on reliability.In this work, we evaluate the incidence of SFUs on the reliability of GPUs when affected by soft errors. First, we analyze the impact of SFU cores on the GPU’s reliability and the running workloads. We resort to applications configured to use or not the SFU cores and evaluate the effect of soft errors by using a software-based fault injection environment (NVBITFI) in an NVIDIA Ampere GPU. Then, we focus on evaluating the impact of soft errors arising in the SFUs. A fine-grain RTL evaluation determines the soft error effects on two SFUs architectures for GPUs (’fused’ and ’modular’). The experiments use an open-source GPU (FlexGripPlus) instrumented with both SFU architectures. The results suggest that workloads using SFUs are more vulnerable to faults (from 1 up to 5 orders of magnitude for the analyzed applications). Moreover, the RTL results show that modular SFUs are less vulnerable to faults (in up to 47% for the analyzed workloads) in comparison with fused SFUs (base of commercial devices), so allowing us to identify the more robust SFU architecture.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174057
Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand
Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.
{"title":"Approximate Communication: Balancing Performance, Power, Reliability, and Safety","authors":"Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand","doi":"10.1109/ets56758.2023.10174057","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174057","url":null,"abstract":"Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Efficient distribution of tasks in an SOC between various components of an embedded system affect rate of data exchange between cores and obviously the number and fanout of interconnecting cores. Data rate and interconnect fanouts depend on post-layout wire characteristics that, in the worst-case situation, must be evaluated for abovementioned system level decisions. In this work we are making provisions for avoiding this large gap between high-level decision making and low-level physical properties. IP-core interconnects can be fully characterized by post layout information of the IP-core, load properties, and the number of destination cores they are driving. This information can be back-annotated into abstract system-level interconnect models to be used by core integrators for design space exploration (DSE). Fanout and/or frequency of operation of an IP-core can be decided by this DSE environment. In this work, we propose a machine-learning based methodology that uses signoff parasitic information and the actual wire data to generate the dataset and train a model. The model was evaluated in fast high-level SystemC environment for two RISC-V based processors in two SoCs. The models were 26 times faster than the low-level simulations with a crosstalk fault coverage of 1.5% error.
{"title":"Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction","authors":"Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Z. Navabi","doi":"10.1109/ETS56758.2023.10173987","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173987","url":null,"abstract":"Efficient distribution of tasks in an SOC between various components of an embedded system affect rate of data exchange between cores and obviously the number and fanout of interconnecting cores. Data rate and interconnect fanouts depend on post-layout wire characteristics that, in the worst-case situation, must be evaluated for abovementioned system level decisions. In this work we are making provisions for avoiding this large gap between high-level decision making and low-level physical properties. IP-core interconnects can be fully characterized by post layout information of the IP-core, load properties, and the number of destination cores they are driving. This information can be back-annotated into abstract system-level interconnect models to be used by core integrators for design space exploration (DSE). Fanout and/or frequency of operation of an IP-core can be decided by this DSE environment. In this work, we propose a machine-learning based methodology that uses signoff parasitic information and the actual wire data to generate the dataset and train a model. The model was evaluated in fast high-level SystemC environment for two RISC-V based processors in two SoCs. The models were 26 times faster than the low-level simulations with a crosstalk fault coverage of 1.5% error.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130787792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174131
Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl
With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.
{"title":"Counterfeit Detection by Semiconductor Process Technology Inspection","authors":"Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl","doi":"10.1109/ETS56758.2023.10174131","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174131","url":null,"abstract":"With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"260 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114008548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：