Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174099
J. Anders, Pablo Andreu, B. Becker, S. Becker, R. Cantoro, N. I. Deligiannis, N. Elhamawy, Tobias Faller, Carles Hernández, N. Mentens, Mahnaz Namazi Rizi, I. Polian, Abolfazl Sajadi, Mathias Sauer, Denis Schwachhofer, M. Reorda, T. Stefanov, I. Tuzov, S. Wagner, N. Zidarič
With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.
{"title":"A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors","authors":"J. Anders, Pablo Andreu, B. Becker, S. Becker, R. Cantoro, N. I. Deligiannis, N. Elhamawy, Tobias Faller, Carles Hernández, N. Mentens, Mahnaz Namazi Rizi, I. Polian, Abolfazl Sajadi, Mathias Sauer, Denis Schwachhofer, M. Reorda, T. Stefanov, I. Tuzov, S. Wagner, N. Zidarič","doi":"10.1109/ETS56758.2023.10174099","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174099","url":null,"abstract":"With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174027
{"title":"Silicon Lifecycle Redefines Design for Test","authors":"","doi":"10.1109/ets56758.2023.10174027","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174027","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125730042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173957
G. Gavarini, A. Ruospo, Ernesto Sánchez
In recent years, the reliability of Deep Neural Networks (DNN) has become the focus of an increasing number of research activities. In particular, researchers have focused on understanding how a DNN behaves when the underlying hardware is affected by a fault. This is a challenging task: slight changes in a network architecture can significantly impact how the network reacts to faults. There are several approaches to simulate the behaviour of a faulty network: the most accurate one is to perform low-level fault simulations. Nonetheless, this task is very time-consuming and costly to be implemented. Even though the injection time can be reduced by injecting faults at the application level, for sufficiently large networks, this time is still very high, requiring weeks to complete a single simulation. This work aims at providing a fast and accurate solution for injecting software-level faults in a DNN that is independent of its architecture and does not require any modification to its structure. For this reason, this paper introduces SCI-FI, a Smart, aCcurate and unIntrusive Fault-Injector. SCI-FI smartly reduces the fault injection time required for a complete fault simulation of the network by taking advantage of two fundamental mechanisms: Fault Dropping and Delayed Start. Experimental results from various ResNet, DenseNet and EfficientNet architectures targeting the CIFAR-10 and ImageNet datasets show that combining these techniques drastically reduces the simulation time, which can last up to 70% less.
{"title":"SCI-FI: a Smart, aCcurate and unIntrusive Fault-Injector for Deep Neural Networks","authors":"G. Gavarini, A. Ruospo, Ernesto Sánchez","doi":"10.1109/ETS56758.2023.10173957","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173957","url":null,"abstract":"In recent years, the reliability of Deep Neural Networks (DNN) has become the focus of an increasing number of research activities. In particular, researchers have focused on understanding how a DNN behaves when the underlying hardware is affected by a fault. This is a challenging task: slight changes in a network architecture can significantly impact how the network reacts to faults. There are several approaches to simulate the behaviour of a faulty network: the most accurate one is to perform low-level fault simulations. Nonetheless, this task is very time-consuming and costly to be implemented. Even though the injection time can be reduced by injecting faults at the application level, for sufficiently large networks, this time is still very high, requiring weeks to complete a single simulation. This work aims at providing a fast and accurate solution for injecting software-level faults in a DNN that is independent of its architecture and does not require any modification to its structure. For this reason, this paper introduces SCI-FI, a Smart, aCcurate and unIntrusive Fault-Injector. SCI-FI smartly reduces the fault injection time required for a complete fault simulation of the network by taking advantage of two fundamental mechanisms: Fault Dropping and Delayed Start. Experimental results from various ResNet, DenseNet and EfficientNet architectures targeting the CIFAR-10 and ImageNet datasets show that combining these techniques drastically reduces the simulation time, which can last up to 70% less.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130381126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174184
{"title":"ETS 2023 Distinguished Service Award","authors":"","doi":"10.1109/ets56758.2023.10174184","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174184","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129913216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173976
Ferhat Can Ataman, Mohammad Aladsani, G. Trichopoulos, Chethan Kumar Y.B., S. Ozev
Hardware imperfections and environmental factors create mismatches between transmit and receive paths. In MIMO mm-Wave radars, determining and eliminating gain and phase mismatches are required to increase the overall accuracy of range and angle of arrival (AoA) estimation. Measurement of mismatches, particularly phase mismatch, requires complex test setups and external equipment, such as a network analyzer. This paper proposes an on-chip (or on-board) measurement method for mm-Wave radars to determine the mismatches using RF power detectors. The proposed method relies on mutual coupling between transmitter and receiver antennas. A detailed mathematical analysis of the proposed method along with boundary conditions is presented. Simulations and hardware measurements using a cascaded mm-Wave radar device shows that the proposed phase mismatch extraction technique provides very accurate results within defined boundary conditions.
{"title":"Mismatch Measurement for MIMO mm-Wave Radars via Simple Power Monitors","authors":"Ferhat Can Ataman, Mohammad Aladsani, G. Trichopoulos, Chethan Kumar Y.B., S. Ozev","doi":"10.1109/ETS56758.2023.10173976","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173976","url":null,"abstract":"Hardware imperfections and environmental factors create mismatches between transmit and receive paths. In MIMO mm-Wave radars, determining and eliminating gain and phase mismatches are required to increase the overall accuracy of range and angle of arrival (AoA) estimation. Measurement of mismatches, particularly phase mismatch, requires complex test setups and external equipment, such as a network analyzer. This paper proposes an on-chip (or on-board) measurement method for mm-Wave radars to determine the mismatches using RF power detectors. The proposed method relies on mutual coupling between transmitter and receiver antennas. A detailed mathematical analysis of the proposed method along with boundary conditions is presented. Simulations and hardware measurements using a cascaded mm-Wave radar device shows that the proposed phase mismatch extraction technique provides very accurate results within defined boundary conditions.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115250550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174129
S. L. Tweehuysen, G. Adriaans, M. Gomony
With Integrated Circuit (IC) designs becoming larger and more complex, there is a growing risk of errors in the Register-Transfer Layer (RTL) implementation. Stimuli generation to achieve high coverage in functional verification is paramount for finding these errors and preventing them from ending up in the final design. Several custom methods have been proposed for stimuli generation to reduce functional testing duration of RTL designs, while more flexible or generic methods could reduce verification time significantly by supporting larger range of RTL designs. This paper proposes a novel flexible stimuli generation technique by using reinforcement learning with an Actor-Critic model. Our benchmarking results showed that the proposed method achieves a higher coverage than baseline solution for a diverse range of RTL designs, making it a valuable addition to test automation tool-flow.
{"title":"Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model","authors":"S. L. Tweehuysen, G. Adriaans, M. Gomony","doi":"10.1109/ETS56758.2023.10174129","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174129","url":null,"abstract":"With Integrated Circuit (IC) designs becoming larger and more complex, there is a growing risk of errors in the Register-Transfer Layer (RTL) implementation. Stimuli generation to achieve high coverage in functional verification is paramount for finding these errors and preventing them from ending up in the final design. Several custom methods have been proposed for stimuli generation to reduce functional testing duration of RTL designs, while more flexible or generic methods could reduce verification time significantly by supporting larger range of RTL designs. This paper proposes a novel flexible stimuli generation technique by using reinforcement learning with an Actor-Critic model. Our benchmarking results showed that the proposed method achieves a higher coverage than baseline solution for a diverse range of RTL designs, making it a valuable addition to test automation tool-flow.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174193
{"title":"ETS 2023 Steering and Program Committees","authors":"","doi":"10.1109/ets56758.2023.10174193","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174193","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116826656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174229
Anurup Saha, C. Amarnath, A. Chatterjee
Spiking Neural Networks (SNNs) can be implemented with power-efficient digital as well as analog circuitry. However, in Resistive RAM (RRAM) based SNN accelerators, synapse weights programmed into the crossbar can differ from their ideal values due to defects and programming errors, degrading inference accuracy. In addition, circuit nonidealities within analog spiking neurons that alter the neuron spiking rate (modeled by variations in neuron firing threshold) can degrade SNN inference accuracy when the value of inference time steps (ITSteps) of SNN is set to a critical minimum that maximizes network throughput. We first develop a recursive linearized check to detect synapse weight errors with high sensitivity. This triggers a correction methodology which sets out-of-range synapse values to zero. For correcting the effects of firing threshold variations, we develop a test methodology that calibrates the extent of such variations. This is then used to proportionally increase inference time steps during inference for chips with higher variation. Experiments on a variety of SNNs prove the viability of the proposed resilience methods.
{"title":"A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural Networks","authors":"Anurup Saha, C. Amarnath, A. Chatterjee","doi":"10.1109/ETS56758.2023.10174229","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174229","url":null,"abstract":"Spiking Neural Networks (SNNs) can be implemented with power-efficient digital as well as analog circuitry. However, in Resistive RAM (RRAM) based SNN accelerators, synapse weights programmed into the crossbar can differ from their ideal values due to defects and programming errors, degrading inference accuracy. In addition, circuit nonidealities within analog spiking neurons that alter the neuron spiking rate (modeled by variations in neuron firing threshold) can degrade SNN inference accuracy when the value of inference time steps (ITSteps) of SNN is set to a critical minimum that maximizes network throughput. We first develop a recursive linearized check to detect synapse weight errors with high sensitivity. This triggers a correction methodology which sets out-of-range synapse values to zero. For correcting the effects of firing threshold variations, we develop a test methodology that calibrates the extent of such variations. This is then used to proportionally increase inference time steps during inference for chips with higher variation. Experiments on a variety of SNNs prove the viability of the proposed resilience methods.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115231886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174164
Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, M. Krstic, L. Benini
Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallel-ultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to system-level improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.
{"title":"PULP Fiction No More—Dependable PULP Systems for Space","authors":"Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, M. Krstic, L. Benini","doi":"10.1109/ETS56758.2023.10174164","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174164","url":null,"abstract":"Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallel-ultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to system-level improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129724180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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