Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174110
J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda
1 Currently, Graphics Processing Units (GPUs) are extensively used in several safety-critical domains to support the implementation of complex operations where reliability is a major concern. Some internal cores, such as Special Function Units (SFUs), are increasingly adopted, being crucial to achieving the necessary performance in multimedia, scientific computing, and neural network training. Unfortunately, these cores are highly unexplored in terms of their impact on reliability.In this work, we evaluate the incidence of SFUs on the reliability of GPUs when affected by soft errors. First, we analyze the impact of SFU cores on the GPU’s reliability and the running workloads. We resort to applications configured to use or not the SFU cores and evaluate the effect of soft errors by using a software-based fault injection environment (NVBITFI) in an NVIDIA Ampere GPU. Then, we focus on evaluating the impact of soft errors arising in the SFUs. A fine-grain RTL evaluation determines the soft error effects on two SFUs architectures for GPUs (’fused’ and ’modular’). The experiments use an open-source GPU (FlexGripPlus) instrumented with both SFU architectures. The results suggest that workloads using SFUs are more vulnerable to faults (from 1 up to 5 orders of magnitude for the analyzed applications). Moreover, the RTL results show that modular SFUs are less vulnerable to faults (in up to 47% for the analyzed workloads) in comparison with fused SFUs (base of commercial devices), so allowing us to identify the more robust SFU architecture.
{"title":"Evaluating the Prevalence of SFUs in the Reliability of GPUs","authors":"J. E. R. Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, M. Reorda","doi":"10.1109/ETS56758.2023.10174110","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174110","url":null,"abstract":"1 Currently, Graphics Processing Units (GPUs) are extensively used in several safety-critical domains to support the implementation of complex operations where reliability is a major concern. Some internal cores, such as Special Function Units (SFUs), are increasingly adopted, being crucial to achieving the necessary performance in multimedia, scientific computing, and neural network training. Unfortunately, these cores are highly unexplored in terms of their impact on reliability.In this work, we evaluate the incidence of SFUs on the reliability of GPUs when affected by soft errors. First, we analyze the impact of SFU cores on the GPU’s reliability and the running workloads. We resort to applications configured to use or not the SFU cores and evaluate the effect of soft errors by using a software-based fault injection environment (NVBITFI) in an NVIDIA Ampere GPU. Then, we focus on evaluating the impact of soft errors arising in the SFUs. A fine-grain RTL evaluation determines the soft error effects on two SFUs architectures for GPUs (’fused’ and ’modular’). The experiments use an open-source GPU (FlexGripPlus) instrumented with both SFU architectures. The results suggest that workloads using SFUs are more vulnerable to faults (from 1 up to 5 orders of magnitude for the analyzed applications). Moreover, the RTL results show that modular SFUs are less vulnerable to faults (in up to 47% for the analyzed workloads) in comparison with fused SFUs (base of commercial devices), so allowing us to identify the more robust SFU architecture.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174207
{"title":"ETS 2023 Foreword","authors":"","doi":"10.1109/ets56758.2023.10174207","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174207","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128782051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174057
Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand
Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.
{"title":"Approximate Communication: Balancing Performance, Power, Reliability, and Safety","authors":"Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand","doi":"10.1109/ets56758.2023.10174057","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174057","url":null,"abstract":"Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Efficient distribution of tasks in an SOC between various components of an embedded system affect rate of data exchange between cores and obviously the number and fanout of interconnecting cores. Data rate and interconnect fanouts depend on post-layout wire characteristics that, in the worst-case situation, must be evaluated for abovementioned system level decisions. In this work we are making provisions for avoiding this large gap between high-level decision making and low-level physical properties. IP-core interconnects can be fully characterized by post layout information of the IP-core, load properties, and the number of destination cores they are driving. This information can be back-annotated into abstract system-level interconnect models to be used by core integrators for design space exploration (DSE). Fanout and/or frequency of operation of an IP-core can be decided by this DSE environment. In this work, we propose a machine-learning based methodology that uses signoff parasitic information and the actual wire data to generate the dataset and train a model. The model was evaluated in fast high-level SystemC environment for two RISC-V based processors in two SoCs. The models were 26 times faster than the low-level simulations with a crosstalk fault coverage of 1.5% error.
{"title":"Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction","authors":"Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Z. Navabi","doi":"10.1109/ETS56758.2023.10173987","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173987","url":null,"abstract":"Efficient distribution of tasks in an SOC between various components of an embedded system affect rate of data exchange between cores and obviously the number and fanout of interconnecting cores. Data rate and interconnect fanouts depend on post-layout wire characteristics that, in the worst-case situation, must be evaluated for abovementioned system level decisions. In this work we are making provisions for avoiding this large gap between high-level decision making and low-level physical properties. IP-core interconnects can be fully characterized by post layout information of the IP-core, load properties, and the number of destination cores they are driving. This information can be back-annotated into abstract system-level interconnect models to be used by core integrators for design space exploration (DSE). Fanout and/or frequency of operation of an IP-core can be decided by this DSE environment. In this work, we propose a machine-learning based methodology that uses signoff parasitic information and the actual wire data to generate the dataset and train a model. The model was evaluated in fast high-level SystemC environment for two RISC-V based processors in two SoCs. The models were 26 times faster than the low-level simulations with a crosstalk fault coverage of 1.5% error.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130787792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174131
Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl
With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.
{"title":"Counterfeit Detection by Semiconductor Process Technology Inspection","authors":"Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl","doi":"10.1109/ETS56758.2023.10174131","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174131","url":null,"abstract":"With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114008548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174083
N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero
In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.
{"title":"Semi-Supervised Deep Learning for Microcontroller Performance Screening","authors":"N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/ETS56758.2023.10174083","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174083","url":null,"abstract":"In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174179
C. Cui, Tuanhui Xu, Haitao Fu, Junlin Huang
As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.
{"title":"Physical-aware Interconnect Testing and Repairing of Chiplets","authors":"C. Cui, Tuanhui Xu, Haitao Fu, Junlin Huang","doi":"10.1109/ETS56758.2023.10174179","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174179","url":null,"abstract":"As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121830751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174095
Asimina Koutra, V. Tenentes
High throughput and energy efficient integrated cryptographic hash primitives are important for the continuous integrity checking and tampering detection in secure access management mechanisms of on-chip instrumentation, such as the IJTAG. However, previous SHA-256 cores focus only on throughput. In this paper, we synthesize with a 32 nm CMOS Technology SHA-256 cores that can be integrated in ASICs, and we present insights on their achieved throughput and energy efficiency. Moreover, we present a novel clock-gated design for reducing dynamic power dissipation of SHA-256 cores; and a novel Multi-Vt design for reducing static power dissipation of SHA-256 cores. The proposed designs can achieve upto 25.9% improvement of the energy efficiency of existing SHA-256 designs, without impacting their performed throughput. To the best of our knowledge, this is the first work that applies low power design techniques on SHA-256 cores.
{"title":"High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications","authors":"Asimina Koutra, V. Tenentes","doi":"10.1109/ETS56758.2023.10174095","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174095","url":null,"abstract":"High throughput and energy efficient integrated cryptographic hash primitives are important for the continuous integrity checking and tampering detection in secure access management mechanisms of on-chip instrumentation, such as the IJTAG. However, previous SHA-256 cores focus only on throughput. In this paper, we synthesize with a 32 nm CMOS Technology SHA-256 cores that can be integrated in ASICs, and we present insights on their achieved throughput and energy efficiency. Moreover, we present a novel clock-gated design for reducing dynamic power dissipation of SHA-256 cores; and a novel Multi-Vt design for reducing static power dissipation of SHA-256 cores. The proposed designs can achieve upto 25.9% improvement of the energy efficiency of existing SHA-256 designs, without impacting their performed throughput. To the best of our knowledge, this is the first work that applies low power design techniques on SHA-256 cores.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130237177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174237
Soyed Tuhin Ahmed, R. Rakhmatullin, M. Tahoori
Neural networks (NNs) are a widely-used problem-solving tool, but their high computational and power consumption makes them expensive. Computation-in-Memory (CiM) architecture, which uses resistive non-volatile memories, is a promising solution due to its high energy efficiency. However, manufacturing defects and in-field faults can reduce the reliability and inference accuracy of CiM-implemented neural networks. Existing sophisticated fault detection and tolerance techniques require long downtime for testing and repair. In certain applications, e.g., "always on" NN applications, such downtime may not be acceptable. Thus, in this paper, a low-cost online fault tolerance technique based on local approximations is proposed to ensure continuous neural network operation with acceptable accuracy. Our approach reduces hardware overhead by up to 99.37% compared to conventional redundancy-based approaches while still achieving accuracy within 2% of the trained NNs.
{"title":"Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local Approximation","authors":"Soyed Tuhin Ahmed, R. Rakhmatullin, M. Tahoori","doi":"10.1109/ETS56758.2023.10174237","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174237","url":null,"abstract":"Neural networks (NNs) are a widely-used problem-solving tool, but their high computational and power consumption makes them expensive. Computation-in-Memory (CiM) architecture, which uses resistive non-volatile memories, is a promising solution due to its high energy efficiency. However, manufacturing defects and in-field faults can reduce the reliability and inference accuracy of CiM-implemented neural networks. Existing sophisticated fault detection and tolerance techniques require long downtime for testing and repair. In certain applications, e.g., \"always on\" NN applications, such downtime may not be acceptable. Thus, in this paper, a low-cost online fault tolerance technique based on local approximations is proposed to ensure continuous neural network operation with acceptable accuracy. Our approach reduces hardware overhead by up to 99.37% compared to conventional redundancy-based approaches while still achieving accuracy within 2% of the trained NNs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130141564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174106
Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui
Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.
{"title":"Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs","authors":"Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui","doi":"10.1109/ETS56758.2023.10174106","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174106","url":null,"abstract":"Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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