Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174129
S. L. Tweehuysen, G. Adriaans, M. Gomony
With Integrated Circuit (IC) designs becoming larger and more complex, there is a growing risk of errors in the Register-Transfer Layer (RTL) implementation. Stimuli generation to achieve high coverage in functional verification is paramount for finding these errors and preventing them from ending up in the final design. Several custom methods have been proposed for stimuli generation to reduce functional testing duration of RTL designs, while more flexible or generic methods could reduce verification time significantly by supporting larger range of RTL designs. This paper proposes a novel flexible stimuli generation technique by using reinforcement learning with an Actor-Critic model. Our benchmarking results showed that the proposed method achieves a higher coverage than baseline solution for a diverse range of RTL designs, making it a valuable addition to test automation tool-flow.
{"title":"Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model","authors":"S. L. Tweehuysen, G. Adriaans, M. Gomony","doi":"10.1109/ETS56758.2023.10174129","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174129","url":null,"abstract":"With Integrated Circuit (IC) designs becoming larger and more complex, there is a growing risk of errors in the Register-Transfer Layer (RTL) implementation. Stimuli generation to achieve high coverage in functional verification is paramount for finding these errors and preventing them from ending up in the final design. Several custom methods have been proposed for stimuli generation to reduce functional testing duration of RTL designs, while more flexible or generic methods could reduce verification time significantly by supporting larger range of RTL designs. This paper proposes a novel flexible stimuli generation technique by using reinforcement learning with an Actor-Critic model. Our benchmarking results showed that the proposed method achieves a higher coverage than baseline solution for a diverse range of RTL designs, making it a valuable addition to test automation tool-flow.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174019
{"title":"ETS 2023 Blank Page","authors":"","doi":"10.1109/ets56758.2023.10174019","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174019","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116611804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174193
{"title":"ETS 2023 Steering and Program Committees","authors":"","doi":"10.1109/ets56758.2023.10174193","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174193","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116826656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174229
Anurup Saha, C. Amarnath, A. Chatterjee
Spiking Neural Networks (SNNs) can be implemented with power-efficient digital as well as analog circuitry. However, in Resistive RAM (RRAM) based SNN accelerators, synapse weights programmed into the crossbar can differ from their ideal values due to defects and programming errors, degrading inference accuracy. In addition, circuit nonidealities within analog spiking neurons that alter the neuron spiking rate (modeled by variations in neuron firing threshold) can degrade SNN inference accuracy when the value of inference time steps (ITSteps) of SNN is set to a critical minimum that maximizes network throughput. We first develop a recursive linearized check to detect synapse weight errors with high sensitivity. This triggers a correction methodology which sets out-of-range synapse values to zero. For correcting the effects of firing threshold variations, we develop a test methodology that calibrates the extent of such variations. This is then used to proportionally increase inference time steps during inference for chips with higher variation. Experiments on a variety of SNNs prove the viability of the proposed resilience methods.
{"title":"A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural Networks","authors":"Anurup Saha, C. Amarnath, A. Chatterjee","doi":"10.1109/ETS56758.2023.10174229","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174229","url":null,"abstract":"Spiking Neural Networks (SNNs) can be implemented with power-efficient digital as well as analog circuitry. However, in Resistive RAM (RRAM) based SNN accelerators, synapse weights programmed into the crossbar can differ from their ideal values due to defects and programming errors, degrading inference accuracy. In addition, circuit nonidealities within analog spiking neurons that alter the neuron spiking rate (modeled by variations in neuron firing threshold) can degrade SNN inference accuracy when the value of inference time steps (ITSteps) of SNN is set to a critical minimum that maximizes network throughput. We first develop a recursive linearized check to detect synapse weight errors with high sensitivity. This triggers a correction methodology which sets out-of-range synapse values to zero. For correcting the effects of firing threshold variations, we develop a test methodology that calibrates the extent of such variations. This is then used to proportionally increase inference time steps during inference for chips with higher variation. Experiments on a variety of SNNs prove the viability of the proposed resilience methods.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115231886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174164
Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, M. Krstic, L. Benini
Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallel-ultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to system-level improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.
{"title":"PULP Fiction No More—Dependable PULP Systems for Space","authors":"Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, M. Krstic, L. Benini","doi":"10.1109/ETS56758.2023.10174164","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174164","url":null,"abstract":"Due to their flexibility and openness, the RISC-V ISA and processor architectures have emerged as notable contenders in various application domains. Their advantages over commercial solutions have attracted the interest of academia and industry and even led to their planned adoption in aeronautics and space. However, in these demanding environments, system reliability is of paramount importance. To address this issue, this paper presents an overview of several hardware-centric approaches for developing reliable systems based on the parallel-ultra low power (PULP) open-source RISC-V hardware platform. These approaches range from gate-level optimizations to system-level improvements and highlight the versatility of the PULP architecture and its potential as a viable architecture for developing various aerospace platforms.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129724180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10173956
{"title":"ETS23 Sponsors and Organizers","authors":"","doi":"10.1109/ets56758.2023.10173956","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10173956","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174024
G. Léger, A. Ginés, E. Peralías, Valentín Gutiérrez, C. Dominguez, M. A. Jalón, L. Carranza
One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.
{"title":"A Single-Event Latchup setup for high-precision AMS circuits","authors":"G. Léger, A. Ginés, E. Peralías, Valentín Gutiérrez, C. Dominguez, M. A. Jalón, L. Carranza","doi":"10.1109/ETS56758.2023.10174024","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174024","url":null,"abstract":"One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174063
Alper Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, S. Sezer, M. Ottavi, O. Ergin
Instruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC’s fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processing-in-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-to-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.
{"title":"DEV-PIM: Dynamic Execution Validation with Processing-in-Memory","authors":"Alper Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, S. Sezer, M. Ottavi, O. Ergin","doi":"10.1109/ETS56758.2023.10174063","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174063","url":null,"abstract":"Instruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC’s fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processing-in-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-to-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127432567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174113
M. Fieback, Filip Bradaric, M. Taouil, S. Hamdioui
Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.
{"title":"Online Fault Detection and Diagnosis in RRAM","authors":"M. Fieback, Filip Bradaric, M. Taouil, S. Hamdioui","doi":"10.1109/ETS56758.2023.10174113","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174113","url":null,"abstract":"Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174093
J. Rajski, Maciej Trawka, J. Tyszer, Bartosz Wlodarczak
Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.
{"title":"Hybrid Ring Generators for In-System Test Applications","authors":"J. Rajski, Maciej Trawka, J. Tyszer, Bartosz Wlodarczak","doi":"10.1109/ETS56758.2023.10174093","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174093","url":null,"abstract":"Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115546638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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