Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174155
Zhang Tao, M. Tehranipoor, Farimah Farahmandi
FPGAs have been widely deployed in critical applications ranging from consumer electronics to spacecraft while the mainstream vendors refuse to disclose the details of their configuration bitstream format for security considerations but obstruct benign applications at the same time. Despite several bitstream reverse engineering solutions being proposed to reconstruct the bitstream formats, the state-of-the-art techniques typically require at least days to partially retrieve the architecture-specific bitstream format for a single (small) FPGA model. In this paper, we propose our BitFREE methodology which targets the most market-dominating Xilinx devices to reverse engineer the majority of bitstream formats of all models in different FPGA families at the time in the order of minutes by utilizing the correlation between FPGA architecture and the configuration memory map to decompose the configuration frames into more fine-grained segments for intelligent parallel analysis instead of directly analyzing entire bitstreams serially like other works. We demonstrate the high accuracy of BitFREE by recovering the information precisely from bitstreams of covered FPGA models. Also, we introduce two security applications of BitFREE, i.e., routing-level bitstream tampering and malicious ring oscillator circuitry detection, to shed light on the broad usage of bitstream reverse engineering in the hardware security domain.
{"title":"BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering","authors":"Zhang Tao, M. Tehranipoor, Farimah Farahmandi","doi":"10.1109/ETS56758.2023.10174155","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174155","url":null,"abstract":"FPGAs have been widely deployed in critical applications ranging from consumer electronics to spacecraft while the mainstream vendors refuse to disclose the details of their configuration bitstream format for security considerations but obstruct benign applications at the same time. Despite several bitstream reverse engineering solutions being proposed to reconstruct the bitstream formats, the state-of-the-art techniques typically require at least days to partially retrieve the architecture-specific bitstream format for a single (small) FPGA model. In this paper, we propose our BitFREE methodology which targets the most market-dominating Xilinx devices to reverse engineer the majority of bitstream formats of all models in different FPGA families at the time in the order of minutes by utilizing the correlation between FPGA architecture and the configuration memory map to decompose the configuration frames into more fine-grained segments for intelligent parallel analysis instead of directly analyzing entire bitstreams serially like other works. We demonstrate the high accuracy of BitFREE by recovering the information precisely from bitstreams of covered FPGA models. Also, we introduce two security applications of BitFREE, i.e., routing-level bitstream tampering and malicious ring oscillator circuitry detection, to shed light on the broad usage of bitstream reverse engineering in the hardware security domain.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123023662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174179
C. Cui, Tuanhui Xu, Haitao Fu, Junlin Huang
As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.
{"title":"Physical-aware Interconnect Testing and Repairing of Chiplets","authors":"C. Cui, Tuanhui Xu, Haitao Fu, Junlin Huang","doi":"10.1109/ETS56758.2023.10174179","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174179","url":null,"abstract":"As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121830751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174083
N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero
In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.
{"title":"Semi-Supervised Deep Learning for Microcontroller Performance Screening","authors":"N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/ETS56758.2023.10174083","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174083","url":null,"abstract":"In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174106
Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui
Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.
{"title":"Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs","authors":"Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui","doi":"10.1109/ETS56758.2023.10174106","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174106","url":null,"abstract":"Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174237
Soyed Tuhin Ahmed, R. Rakhmatullin, M. Tahoori
Neural networks (NNs) are a widely-used problem-solving tool, but their high computational and power consumption makes them expensive. Computation-in-Memory (CiM) architecture, which uses resistive non-volatile memories, is a promising solution due to its high energy efficiency. However, manufacturing defects and in-field faults can reduce the reliability and inference accuracy of CiM-implemented neural networks. Existing sophisticated fault detection and tolerance techniques require long downtime for testing and repair. In certain applications, e.g., "always on" NN applications, such downtime may not be acceptable. Thus, in this paper, a low-cost online fault tolerance technique based on local approximations is proposed to ensure continuous neural network operation with acceptable accuracy. Our approach reduces hardware overhead by up to 99.37% compared to conventional redundancy-based approaches while still achieving accuracy within 2% of the trained NNs.
{"title":"Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local Approximation","authors":"Soyed Tuhin Ahmed, R. Rakhmatullin, M. Tahoori","doi":"10.1109/ETS56758.2023.10174237","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174237","url":null,"abstract":"Neural networks (NNs) are a widely-used problem-solving tool, but their high computational and power consumption makes them expensive. Computation-in-Memory (CiM) architecture, which uses resistive non-volatile memories, is a promising solution due to its high energy efficiency. However, manufacturing defects and in-field faults can reduce the reliability and inference accuracy of CiM-implemented neural networks. Existing sophisticated fault detection and tolerance techniques require long downtime for testing and repair. In certain applications, e.g., \"always on\" NN applications, such downtime may not be acceptable. Thus, in this paper, a low-cost online fault tolerance technique based on local approximations is proposed to ensure continuous neural network operation with acceptable accuracy. Our approach reduces hardware overhead by up to 99.37% compared to conventional redundancy-based approaches while still achieving accuracy within 2% of the trained NNs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"2204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130141564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174095
Asimina Koutra, V. Tenentes
High throughput and energy efficient integrated cryptographic hash primitives are important for the continuous integrity checking and tampering detection in secure access management mechanisms of on-chip instrumentation, such as the IJTAG. However, previous SHA-256 cores focus only on throughput. In this paper, we synthesize with a 32 nm CMOS Technology SHA-256 cores that can be integrated in ASICs, and we present insights on their achieved throughput and energy efficiency. Moreover, we present a novel clock-gated design for reducing dynamic power dissipation of SHA-256 cores; and a novel Multi-Vt design for reducing static power dissipation of SHA-256 cores. The proposed designs can achieve upto 25.9% improvement of the energy efficiency of existing SHA-256 designs, without impacting their performed throughput. To the best of our knowledge, this is the first work that applies low power design techniques on SHA-256 cores.
{"title":"High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications","authors":"Asimina Koutra, V. Tenentes","doi":"10.1109/ETS56758.2023.10174095","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174095","url":null,"abstract":"High throughput and energy efficient integrated cryptographic hash primitives are important for the continuous integrity checking and tampering detection in secure access management mechanisms of on-chip instrumentation, such as the IJTAG. However, previous SHA-256 cores focus only on throughput. In this paper, we synthesize with a 32 nm CMOS Technology SHA-256 cores that can be integrated in ASICs, and we present insights on their achieved throughput and energy efficiency. Moreover, we present a novel clock-gated design for reducing dynamic power dissipation of SHA-256 cores; and a novel Multi-Vt design for reducing static power dissipation of SHA-256 cores. The proposed designs can achieve upto 25.9% improvement of the energy efficiency of existing SHA-256 designs, without impacting their performed throughput. To the best of our knowledge, this is the first work that applies low power design techniques on SHA-256 cores.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130237177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174131
Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl
With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.
{"title":"Counterfeit Detection by Semiconductor Process Technology Inspection","authors":"Matthias Ludwig, A. Bette, Bernhard Lippmann, G. Sigl","doi":"10.1109/ETS56758.2023.10174131","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174131","url":null,"abstract":"With world-wide distributed semiconductor supply chains and a scarcity of microelectronic products, counterfeit devices are gaining momentum. Sourcing products from trusted providers are the theoretical remedy, yet practice shows the reality. Forged electronics are entering the supply chain at a high rate and pose a threat to safety, reliability, and security. Academia and industry have established various pre- or post-production measures to effectively address this issue partially. Yet, several inadequately covered aspects of the field require improvements. First, this work introduces a rating scheme to enable the effective comparison between anti-counterfeiting methods. Recently published methods are compared using this scheme. Second, a novel, generic, generally applicable prover-verifier attestation framework for post-production anti-counterfeiting methods is established. Third, the work implements a new anti-counterfeit method. By introducing technological individual features, the method incorporates technology intrinsic features of the front-end semiconductor manufacturing process as technology distinctive characteristic. Profile parameters are extracted through pattern recognition and statistical methods which are compared to the expected technologies through distance metrics, allowing an assertion of device authenticity. Finally, the versatility of the method is experimentally validated through real samples. Overall, an accuracy of 100% is reported for seven samples which are checked for authenticity.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"260 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114008548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174107
L. Ammoura, M. Flottes, P. Girard, J. Noel, A. Virazel
The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.
{"title":"Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture","authors":"L. Ammoura, M. Flottes, P. Girard, J. Noel, A. Virazel","doi":"10.1109/ETS56758.2023.10174107","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174107","url":null,"abstract":"The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ets56758.2023.10174187
{"title":"ETS 2022 Best Paper","authors":"","doi":"10.1109/ets56758.2023.10174187","DOIUrl":"https://doi.org/10.1109/ets56758.2023.10174187","url":null,"abstract":"","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173941
Athanasios Xynos, V. Tenentes, Y. Tsiatouhas
Secure computing necessitates hardware root of trust (RoT) integrated in Systems-on-Chips (SoCs) for cryptographic keys generation, authentication and identification. In this paper, we observe that bitflips in SRAM cells that appear while accessing multiple cells from the same bitline, are not stochastic, as previously considered, but systematic. Based on this observation, a novel strong in-memory Physical Unclonable Function (PUF) computation is proposed for harvesting static entropy from SRAM arrays. The proposed design is compatible with existing in-SRAM computing architectures. To verify our PUF operation, we implement a 6T SRAM array model that performs in-memory computing using a 32 nm CMOS Technology, and, through SPICE simulation, we evaluate the proposed PUF performance. The proposed PUF operation achieves uniqueness and uniformity of 49.99%, and 49.74%, respectively, and reliability higher than 97.4% when the temperature is varied from 0°C to 100°C, and higher than 95.2% when the nominal voltage supply is varied by 10%. Furthermore, we explore the scaling of the number of Challenge Response Pairs (CRPs) of the proposed PUF, and we compare it against the state-of-the-art. Our PUF offers orders of magnitude higher number of CRPs, therefore it is suitable for integrated mechanisms that assure secure computing in SoCs.
{"title":"SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs","authors":"Athanasios Xynos, V. Tenentes, Y. Tsiatouhas","doi":"10.1109/ETS56758.2023.10173941","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173941","url":null,"abstract":"Secure computing necessitates hardware root of trust (RoT) integrated in Systems-on-Chips (SoCs) for cryptographic keys generation, authentication and identification. In this paper, we observe that bitflips in SRAM cells that appear while accessing multiple cells from the same bitline, are not stochastic, as previously considered, but systematic. Based on this observation, a novel strong in-memory Physical Unclonable Function (PUF) computation is proposed for harvesting static entropy from SRAM arrays. The proposed design is compatible with existing in-SRAM computing architectures. To verify our PUF operation, we implement a 6T SRAM array model that performs in-memory computing using a 32 nm CMOS Technology, and, through SPICE simulation, we evaluate the proposed PUF performance. The proposed PUF operation achieves uniqueness and uniformity of 49.99%, and 49.74%, respectively, and reliability higher than 97.4% when the temperature is varied from 0°C to 100°C, and higher than 95.2% when the nominal voltage supply is varied by 10%. Furthermore, we explore the scaling of the number of Challenge Response Pairs (CRPs) of the proposed PUF, and we compare it against the state-of-the-art. Our PUF offers orders of magnitude higher number of CRPs, therefore it is suitable for integrated mechanisms that assure secure computing in SoCs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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