Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174176
A. Ruospo, G. Gavarini, A. Porsia, M. Reorda, Ernesto Sánchez, R. Mariani, J. Aribido, J. Athavale
The widespread use of artificial intelligence (AI)-based systems has raised several concerns about their deployment in safety-critical systems. Industry standards, such as ISO26262 for automotive, require detecting hardware faults during the mission of the device. Similarly, new standards are being released concerning the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for the infield testing of the hardware executing AI applications; however, when used in applications such as Convolutional Neural Networks (CNNs) in image processing tasks, their usage may increase the hardware cost and affect the application performances. In this paper, for the very first time, a methodology to develop high-quality test images, to be interleaved with the normal inference process of the CNN application is proposed. An Image Test Library (ITL) is developed targeting the on-line test of GPU functional units. The proposed approach does not require changing the actual CNN (thus incurring in costly memory loading operations) since it is able to exploit the actual CNN structure. Experimental results show that a 6-image ITL is able to achieve about 95% of stuck-at test coverage on the floating-point multipliers in a GPU. The obtained ITL requires a very low test application time, as well as a very low memory space for storing the test images and the golden test responses.
基于人工智能(AI)的系统的广泛使用引发了人们对其在安全关键系统中的部署的担忧。汽车行业的ISO26262等标准要求在设备执行任务期间检测硬件故障。同样，有关人工智能系统功能安全的新标准正在发布(例如，ISO/IEC CD TR 5469)。已经提出了硬件解决方案，用于执行AI应用程序的硬件的内场测试;然而，当在图像处理任务中使用卷积神经网络(cnn)等应用时，它们的使用可能会增加硬件成本并影响应用性能。本文首次提出了一种开发高质量测试图像的方法，该图像与CNN应用的正常推理过程交织在一起。针对GPU功能单元的在线测试，开发了图像测试库(ITL)。所提出的方法不需要改变实际的CNN(从而导致昂贵的内存加载操作)，因为它能够利用实际的CNN结构。实验结果表明，6幅图像的ITL能够在GPU的浮点乘法器上达到95%的卡滞测试覆盖率。获得的ITL需要非常低的测试应用程序时间，以及用于存储测试图像和黄金测试响应的非常低的内存空间。
{"title":"Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs","authors":"A. Ruospo, G. Gavarini, A. Porsia, M. Reorda, Ernesto Sánchez, R. Mariani, J. Aribido, J. Athavale","doi":"10.1109/ETS56758.2023.10174176","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174176","url":null,"abstract":"The widespread use of artificial intelligence (AI)-based systems has raised several concerns about their deployment in safety-critical systems. Industry standards, such as ISO26262 for automotive, require detecting hardware faults during the mission of the device. Similarly, new standards are being released concerning the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for the infield testing of the hardware executing AI applications; however, when used in applications such as Convolutional Neural Networks (CNNs) in image processing tasks, their usage may increase the hardware cost and affect the application performances. In this paper, for the very first time, a methodology to develop high-quality test images, to be interleaved with the normal inference process of the CNN application is proposed. An Image Test Library (ITL) is developed targeting the on-line test of GPU functional units. The proposed approach does not require changing the actual CNN (thus incurring in costly memory loading operations) since it is able to exploit the actual CNN structure. Experimental results show that a 6-image ITL is able to achieve about 95% of stuck-at test coverage on the floating-point multipliers in a GPU. The obtained ITL requires a very low test application time, as well as a very low memory space for storing the test images and the golden test responses.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121789799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173954
Francesco Lorenzelli, A. Elsayed, C. Godfrin, A. Grill, S. Kubicek, Ruoyu Li, M. Stucchi, D. Wan, K. D. Greve, E. Marinissen, G. Gielen
Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.
{"title":"Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications","authors":"Francesco Lorenzelli, A. Elsayed, C. Godfrin, A. Grill, S. Kubicek, Ruoyu Li, M. Stucchi, D. Wan, K. D. Greve, E. Marinissen, G. Gielen","doi":"10.1109/ETS56758.2023.10173954","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173954","url":null,"abstract":"Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133402575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174150
Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Goerschwin Fey
For integrated circuits in vehicular systems, ISO 26262 requires fault injection. Failure modes in natural language specify potential malfunctions of components in an abstract system model. Fault injection in system models ensures that safety mechanisms are effective. This causes a gap in the design process as fault injection campaigns must be derived manually.We introduce the framework FINaL that drives high-level Fault Injection campaigns with Natural Language. FINaL starts from an abstract system model in SysML, requirements, and failure modes described in natural language. We explain how FINaL automatically derives the parameters required for fault injection campaigns on virtual prototypes in SystemC. After training on a simple reference design, experimental results demonstrate that 20% up to 67% of the failure modes for a productive design can automatically be handled.
{"title":"FINaL: Driving High-Level Fault Injection Campaigns with Natural Language","authors":"Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Goerschwin Fey","doi":"10.1109/ETS56758.2023.10174150","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174150","url":null,"abstract":"For integrated circuits in vehicular systems, ISO 26262 requires fault injection. Failure modes in natural language specify potential malfunctions of components in an abstract system model. Fault injection in system models ensures that safety mechanisms are effective. This causes a gap in the design process as fault injection campaigns must be derived manually.We introduce the framework FINaL that drives high-level Fault Injection campaigns with Natural Language. FINaL starts from an abstract system model in SysML, requirements, and failure modes described in natural language. We explain how FINaL automatically derives the parameters required for fault injection campaigns on virtual prototypes in SystemC. After training on a simple reference design, experimental results demonstrate that 20% up to 67% of the failure modes for a productive design can automatically be handled.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114622077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10173861
Jayeeta Chaudhuri, K. Chakrabarty
The popularity of cloud computing has led to increasing demand for efficient and scalable hardware. Multitenant FPGAs are becoming popular because of their ability to provide high performance and flexibility, yet being cost-effective. While multiple tenants have the ability to configure the same FPGA with customized modules, several security vulnerabilities can be exploited by adversaries. Attackers can use an FPGA to perform malicious actions, such as injecting malicious bitstreams and launching denial-of-service attacks. We propose a two-tier machine learning framework that first detects malicious features from an FPGA bitstream and then performs criticality analysis to evaluate the severity of potentially malicious ring oscillators (ROs) configured by that bitstream. The latter step is crucial as it ensures the security of FPGAs from voltage and power-based attacks and also reduces the risk of inappropriately blocking benign RO-based circuits from FPGA configuration. The proposed framework is evaluated using a diverse set of real-world bitstreams. We achieve an accuracy of 100% in detecting malicious bitstreams and an accuracy of 96.55% in detecting malicious bitstreams that are critical.
{"title":"Criticality Analysis of Ring Oscillators in FPGA Bitstreams *","authors":"Jayeeta Chaudhuri, K. Chakrabarty","doi":"10.1109/ETS56758.2023.10173861","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173861","url":null,"abstract":"The popularity of cloud computing has led to increasing demand for efficient and scalable hardware. Multitenant FPGAs are becoming popular because of their ability to provide high performance and flexibility, yet being cost-effective. While multiple tenants have the ability to configure the same FPGA with customized modules, several security vulnerabilities can be exploited by adversaries. Attackers can use an FPGA to perform malicious actions, such as injecting malicious bitstreams and launching denial-of-service attacks. We propose a two-tier machine learning framework that first detects malicious features from an FPGA bitstream and then performs criticality analysis to evaluate the severity of potentially malicious ring oscillators (ROs) configured by that bitstream. The latter step is crucial as it ensures the security of FPGAs from voltage and power-based attacks and also reduces the risk of inappropriately blocking benign RO-based circuits from FPGA configuration. The proposed framework is evaluated using a diverse set of real-world bitstreams. We achieve an accuracy of 100% in detecting malicious bitstreams and an accuracy of 96.55% in detecting malicious bitstreams that are critical.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174000
Yan Ji, Ruize Wang, Kalle Ngo, E. Dubrova, Linus Backlund
CRYSTALS-Kyber has been recently selected by the NIST as a new public-key encryption and key-establishment algorithm to be standardized. This makes it important to assess how well CRYSTALS-Kyber implementations withstand side-channel attacks. Software implementations of CRYSTALS-Kyber have already been analyzed and the discovered vulnerabilities were patched in the subsequently released versions. In this paper, we present a profiling side-channel attack on a hardware implementation of CRYSTALS-Kyber. Since hardware implementations carry out computations in parallel, they are typically more difficult to break than their software counterparts. We demonstrate a successful message (session key) recovery attack on a Xilinx Artix-7 FPGA implementation of CRYSTALS-Kyber by deep learning-based power analysis. Our results indicate that currently available hardware implementations of CRYSTALS-Kyber need better protection against side-channel attacks.
{"title":"A Side-Channel Attack on a Hardware Implementation of CRYSTALS-Kyber","authors":"Yan Ji, Ruize Wang, Kalle Ngo, E. Dubrova, Linus Backlund","doi":"10.1109/ETS56758.2023.10174000","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174000","url":null,"abstract":"CRYSTALS-Kyber has been recently selected by the NIST as a new public-key encryption and key-establishment algorithm to be standardized. This makes it important to assess how well CRYSTALS-Kyber implementations withstand side-channel attacks. Software implementations of CRYSTALS-Kyber have already been analyzed and the discovered vulnerabilities were patched in the subsequently released versions. In this paper, we present a profiling side-channel attack on a hardware implementation of CRYSTALS-Kyber. Since hardware implementations carry out computations in parallel, they are typically more difficult to break than their software counterparts. We demonstrate a successful message (session key) recovery attack on a Xilinx Artix-7 FPGA implementation of CRYSTALS-Kyber by deep learning-based power analysis. Our results indicate that currently available hardware implementations of CRYSTALS-Kyber need better protection against side-channel attacks.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127804266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-22DOI: 10.1109/ETS56758.2023.10174126
Giorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, P. Scaramuzza, R. Ullmann
Embedded System-on-Chip (SoC) memory requirements in the Automotive industry are constantly growing. For this reason, memories occupy a significant part of Automotive SoC’s die area, increasing the defect probability inside the embedded storage. Automotive SoC manufacturers need to deeply test their embedded memories as they are one of the significant contributors to the yield of their devices. The test effort increases for the characterization of new technologies and new families of devices that need to be characterized by the manufacturers. These tests generate a massive quantity of diagnostic information that is incredibly valuable for designers and technology experts. This diagnostic information can be analyzed to identify and correct possible weaknesses and misbehavior. The easiest way to collect memory diagnostic information consists of failure bitmaps in which each fault is saved as coordinates. This method is the simplest solution to implement. However, logging the coordinates of every fault may generate an unmanageable quantity of data. This problem is exacerbated when there is an on-chip limitation on the amount of data that can be saved or transmitted to the external world.This paper presents an optimized on-chip compression algorithm that allows to reduce the required on-chip memory to store diagnostic information during embedded memory testing. This solution allows the reconstruction of a failure bitmap, generating a topological representation of the density of the failings bits in the embedded on-chip memory. The proposed approach effectively reduces the used storage to a fraction with respect to the one used by the original failing bitmap. The algorithm uses a coordinates-based approach, in which the memory is logically divided into equally divided sectors. The small time overhead introduced by the algorithm is compensated by the ability to achieve optimal space utilization.
{"title":"Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip","authors":"Giorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, P. Scaramuzza, R. Ullmann","doi":"10.1109/ETS56758.2023.10174126","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174126","url":null,"abstract":"Embedded System-on-Chip (SoC) memory requirements in the Automotive industry are constantly growing. For this reason, memories occupy a significant part of Automotive SoC’s die area, increasing the defect probability inside the embedded storage. Automotive SoC manufacturers need to deeply test their embedded memories as they are one of the significant contributors to the yield of their devices. The test effort increases for the characterization of new technologies and new families of devices that need to be characterized by the manufacturers. These tests generate a massive quantity of diagnostic information that is incredibly valuable for designers and technology experts. This diagnostic information can be analyzed to identify and correct possible weaknesses and misbehavior. The easiest way to collect memory diagnostic information consists of failure bitmaps in which each fault is saved as coordinates. This method is the simplest solution to implement. However, logging the coordinates of every fault may generate an unmanageable quantity of data. This problem is exacerbated when there is an on-chip limitation on the amount of data that can be saved or transmitted to the external world.This paper presents an optimized on-chip compression algorithm that allows to reduce the required on-chip memory to store diagnostic information during embedded memory testing. This solution allows the reconstruction of a failure bitmap, generating a topological representation of the density of the failings bits in the embedded on-chip memory. The proposed approach effectively reduces the used storage to a fraction with respect to the one used by the original failing bitmap. The algorithm uses a coordinates-based approach, in which the memory is logically divided into equally divided sectors. The small time overhead introduced by the algorithm is compensated by the ability to achieve optimal space utilization.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127118761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-04DOI: 10.1109/ETS56758.2023.10173974
F. Pavanello, Cédric Marchand, I. O’Connor, R. Orobtchouk, F. Mandorlo, X. Letartre, S. Cueff, E. Vatajelu, G. D. Natale, B. Cluzel, A. Coillet, B. Charbonnier, P. Noé, Frantisek Kavan, M. Zoldak, Michal Szaj, P. Bienstman, T. Vaerenbergh, U. Rührmair, Paulo F. Flores, L. G. Silva, R. Chaves, Luis Miguel Silveira, M. Ceccato, D. Gizopoulos, G. Papadimitriou, Vasileios Karakostas, Axel Brando, F. Cazorla, Ramon Canal, P. Closas, Adria Gusi-Amigo, P. Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, S. Carlo, A. Savino
This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.
本特别会议论文介绍了Horizon Europe NEUROPULS项目，该项目旨在利用增强硅光子技术开发安全节能的RISC-V接口神经形态加速器。我们的方法旨在开发一个增强型硅光子平台，一个fpga驱动的risc - v连接的计算平台，以及一个完整的仿真平台，以演示神经形态加速器的功能。特别是，它们的主要优点和局限性将涉及到每个平台的基础技术。然后，我们将讨论边缘计算应用的三个目标用例:全球国家卫星系统(GNSS)抗干扰、自动驾驶和边缘设备中的异常检测。最后，我们将讨论独立加速器实现和项目用例的可靠性和安全性方面。
{"title":"EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS","authors":"F. Pavanello, Cédric Marchand, I. O’Connor, R. Orobtchouk, F. Mandorlo, X. Letartre, S. Cueff, E. Vatajelu, G. D. Natale, B. Cluzel, A. Coillet, B. Charbonnier, P. Noé, Frantisek Kavan, M. Zoldak, Michal Szaj, P. Bienstman, T. Vaerenbergh, U. Rührmair, Paulo F. Flores, L. G. Silva, R. Chaves, Luis Miguel Silveira, M. Ceccato, D. Gizopoulos, G. Papadimitriou, Vasileios Karakostas, Axel Brando, F. Cazorla, Ramon Canal, P. Closas, Adria Gusi-Amigo, P. Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, S. Carlo, A. Savino","doi":"10.1109/ETS56758.2023.10173974","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173974","url":null,"abstract":"This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126741012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-03DOI: 10.1109/ETS56758.2023.10174216
Marti Alonso, David Andreu, R. Canal, S. Carlo, C. Chenet, Juanjo Costa, Andreu Girones, D. Gizopoulos, Vasileios Karakostas, Beatriz Otero, G. Papadimitriou, Eva Rodríguez, A. Savino
Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services. This software stack is intended to have the same level of performance as the x86 architecture, which is currently dominant in the cloud computing industry. In addition, the project aims to create a powerful virtual execution environment that can be used for software development, validation, verification, and testing. The virtual environment will consider the relevant RISC-V ISA extensions required for cloud deployment. Commercial cloud systems use hardware features currently unavailable in RISC-V virtual environments, including virtualization, cryptography, and vectorization. To address this, Vitamin-V will support these features in three virtual environments: QEMU, gem5, and cloud-FPGA prototype platforms. The project will focus on providing support for EPI-based RISC-V designs for both the main CPUs and cloud-important accelerators, such as memory compression. The project will add the compiler (LLVM-based) and toolchain support for the ISA extensions. Moreover, Vitamin-V will develop novel approaches for validating, verifying, and testing software trustworthiness. This paper focuses on the plans and visions that the Vitamin-V project has to support validation, verification, and testing for cloud applications, particularly emphasizing the hardware support that will be provided.
{"title":"Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective","authors":"Marti Alonso, David Andreu, R. Canal, S. Carlo, C. Chenet, Juanjo Costa, Andreu Girones, D. Gizopoulos, Vasileios Karakostas, Beatriz Otero, G. Papadimitriou, Eva Rodríguez, A. Savino","doi":"10.1109/ETS56758.2023.10174216","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174216","url":null,"abstract":"Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services. This software stack is intended to have the same level of performance as the x86 architecture, which is currently dominant in the cloud computing industry. In addition, the project aims to create a powerful virtual execution environment that can be used for software development, validation, verification, and testing. The virtual environment will consider the relevant RISC-V ISA extensions required for cloud deployment. Commercial cloud systems use hardware features currently unavailable in RISC-V virtual environments, including virtualization, cryptography, and vectorization. To address this, Vitamin-V will support these features in three virtual environments: QEMU, gem5, and cloud-FPGA prototype platforms. The project will focus on providing support for EPI-based RISC-V designs for both the main CPUs and cloud-important accelerators, such as memory compression. The project will add the compiler (LLVM-based) and toolchain support for the ISA extensions. Moreover, Vitamin-V will develop novel approaches for validating, verifying, and testing software trustworthiness. This paper focuses on the plans and visions that the Vitamin-V project has to support validation, verification, and testing for cloud applications, particularly emphasizing the hardware support that will be provided.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130693346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-13DOI: 10.1109/ETS56758.2023.10174133
Mohammad Hasan Ahmadilivani, Mahdi Taheri, J. Raik, M. Daneshtalab, M. Jenihhin
Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs’ reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analytical-based methods have been proposed, they are either inaccurate or specific to particular accelerator architectures.In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons’ outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs’ reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges.The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.
{"title":"DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs’ Reliability Assessment","authors":"Mohammad Hasan Ahmadilivani, Mahdi Taheri, J. Raik, M. Daneshtalab, M. Jenihhin","doi":"10.1109/ETS56758.2023.10174133","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174133","url":null,"abstract":"Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs’ reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analytical-based methods have been proposed, they are either inaccurate or specific to particular accelerator architectures.In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons’ outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs’ reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges.The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121406161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-23DOI: 10.1109/ETS56758.2023.10174219
Deniz Kasap, Alessio Carpegna, A. Savino, S. Carlo
Radiation-induced soft errors are one of the most challenging issues in Safety Critical Real-Time Embedded System (SACRES) reliability, usually handled using different flavors of Double Modular Redundancy (DMR) techniques. This solution is becoming unaffordable due to the complexity of modern micro-processors in all domains. This paper addresses the promising field of using Artificial Intelligence (AI) based hardware detectors for soft errors. To create such cores and make them general enough to work with different software applications, micro-architectural attributes are a fascinating option as candidate fault detection features. Several processors already track these features through dedicated Performance Monitoring Unit (PMU). However, there is an open question to understand to what extent they are enough to detect faulty executions. Exploiting the capability of gem5 to simulate real computing systems, perform fault injection experiments, and profile micro-architectural attributes (i.e., gem5 Stats), this paper presents the results of a comprehensive analysis regarding the potential attributes to detect soft errors and the associated models that can be trained with these features.
{"title":"Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study","authors":"Deniz Kasap, Alessio Carpegna, A. Savino, S. Carlo","doi":"10.1109/ETS56758.2023.10174219","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174219","url":null,"abstract":"Radiation-induced soft errors are one of the most challenging issues in Safety Critical Real-Time Embedded System (SACRES) reliability, usually handled using different flavors of Double Modular Redundancy (DMR) techniques. This solution is becoming unaffordable due to the complexity of modern micro-processors in all domains. This paper addresses the promising field of using Artificial Intelligence (AI) based hardware detectors for soft errors. To create such cores and make them general enough to work with different software applications, micro-architectural attributes are a fascinating option as candidate fault detection features. Several processors already track these features through dedicated Performance Monitoring Unit (PMU). However, there is an open question to understand to what extent they are enough to detect faulty executions. Exploiting the capability of gem5 to simulate real computing systems, perform fault injection experiments, and profile micro-architectural attributes (i.e., gem5 Stats), this paper presents the results of a comprehensive analysis regarding the potential attributes to detect soft errors and the associated models that can be trained with these features.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116197133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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