ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)最新文献
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217862
A. Shaari, M. K. Abdullah, S. Shaari
Bi-conically tapered single-mode couplers are fabricated using a fiber fusion coupler workstation. Losses found during fabrication are analyzed for a range of elongation. It is found that longer elongations will lower the losses. Theoretically, the losses are due to the taper paths crossing delineating curves. These losses which occur during tapering process are not really adiabatic if part of the signal power is not guided at the end of tapering process. In other words, taper path will not be inside adiabatic region of cladding guidance. It will cross from core-guidance region into lossy region or non-adiabatic region of cladding guidance.
{"title":"Non-adiabatic losses in fused fiber couplers-experimental findings","authors":"A. Shaari, M. K. Abdullah, S. Shaari","doi":"10.1109/SMELEC.2002.1217862","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217862","url":null,"abstract":"Bi-conically tapered single-mode couplers are fabricated using a fiber fusion coupler workstation. Losses found during fabrication are analyzed for a range of elongation. It is found that longer elongations will lower the losses. Theoretically, the losses are due to the taper paths crossing delineating curves. These losses which occur during tapering process are not really adiabatic if part of the signal power is not guided at the end of tapering process. In other words, taper path will not be inside adiabatic region of cladding guidance. It will cross from core-guidance region into lossy region or non-adiabatic region of cladding guidance.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122904357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217812
A.I. Abdul-Rahim, C. Marsh, P. Ashburn, G. Booker
SiGe Heterojunction Bipolar Transistors (HBTs) require low temperature processing in order to minimize Boron-out diffusion from the base region. In this paper a novel technique of producing low temperature in-situ Phosphorus doped single-crystal silicon emitters for application in SiGe HBTs is presented. The single-crystal silicon was deposited at a temperature of 670/spl deg/C in a UHV-compatible LPCVD cluster tool. Gummel plots of the fabricated transistors show very ideal base and collector current characteristics. An ultra low emitter resistance of 6.6 /spl Omega/./spl mu/m/sup 2/ was also obtained. The very low emitter resistance is due to very low oxygen dose of 5.3/spl times/10/sup 13/ cm/sup -2/ at the single-crystal silicon emitter/silicon substrate interface. The commercial Silvaco TCAD ATHENA and ATLAS were used to model the DC characteristics of the transistor to validate the results.
{"title":"Low temperature in-situ phosphorus doped single-crystal silicon emitters for application in SiGe HBTs","authors":"A.I. Abdul-Rahim, C. Marsh, P. Ashburn, G. Booker","doi":"10.1109/SMELEC.2002.1217812","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217812","url":null,"abstract":"SiGe Heterojunction Bipolar Transistors (HBTs) require low temperature processing in order to minimize Boron-out diffusion from the base region. In this paper a novel technique of producing low temperature in-situ Phosphorus doped single-crystal silicon emitters for application in SiGe HBTs is presented. The single-crystal silicon was deposited at a temperature of 670/spl deg/C in a UHV-compatible LPCVD cluster tool. Gummel plots of the fabricated transistors show very ideal base and collector current characteristics. An ultra low emitter resistance of 6.6 /spl Omega/./spl mu/m/sup 2/ was also obtained. The very low emitter resistance is due to very low oxygen dose of 5.3/spl times/10/sup 13/ cm/sup -2/ at the single-crystal silicon emitter/silicon substrate interface. The commercial Silvaco TCAD ATHENA and ATLAS were used to model the DC characteristics of the transistor to validate the results.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121265819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217825
N. R. Poespawati, A. Udhiarto, D. Hartanto
Solar cell is optimized to convert solar radiation to electrical current with conversion efficiency as high as possible. Due to their superior performance compared to conventional silicon devices we used the Si/sub x/Ge/sub 1-x/ strained layer for increasing the efficiency of solar cell device. By using simulation's tools, i.e. pc1d version 5.6, we investigate and analysis the performance of Si/sub 0.2/Ge/sub 0.8//Si solar cell, especially open circuit voltage, short circuit current, fill factor which will affect the efficiency of the device. We also compare it with conventional silicon solar cell in order to examine their performances and the thickness of both device structures. The Si/sub x/Ge/sub 1-x/ strained layer we applied contents 80% germanium. Results show that by inserting Si/sub 0.2/Ge/sub 0.8/ strained layer in device structure open circuit voltage and short circuit current has been optimal and the thickness of the device compared to conventional silicon solar cell is 1/17 times.
{"title":"The performance of Si/sub 0.2/Ge/sub 0.8//Si solar cell","authors":"N. R. Poespawati, A. Udhiarto, D. Hartanto","doi":"10.1109/SMELEC.2002.1217825","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217825","url":null,"abstract":"Solar cell is optimized to convert solar radiation to electrical current with conversion efficiency as high as possible. Due to their superior performance compared to conventional silicon devices we used the Si/sub x/Ge/sub 1-x/ strained layer for increasing the efficiency of solar cell device. By using simulation's tools, i.e. pc1d version 5.6, we investigate and analysis the performance of Si/sub 0.2/Ge/sub 0.8//Si solar cell, especially open circuit voltage, short circuit current, fill factor which will affect the efficiency of the device. We also compare it with conventional silicon solar cell in order to examine their performances and the thickness of both device structures. The Si/sub x/Ge/sub 1-x/ strained layer we applied contents 80% germanium. Results show that by inserting Si/sub 0.2/Ge/sub 0.8/ strained layer in device structure open circuit voltage and short circuit current has been optimal and the thickness of the device compared to conventional silicon solar cell is 1/17 times.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121482651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217779
M. Sulaiman, N. Khan
A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).
{"title":"A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer","authors":"M. Sulaiman, N. Khan","doi":"10.1109/SMELEC.2002.1217779","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217779","url":null,"abstract":"A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128780921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217881
Jang-Kyoo Shin, Jong-Ho Park, Jung-Hwan Kim, Minho Lee
Human retina is able to detect the edge of the object by effective mechanism. We designed a CMOS vision chip by modeling retinal cells involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip. The vision chip detecting edge information from input image is used for input stage of vision systems. Therefore, the output offset affects the efficiency of entire vision system. In order to eliminate the output offset, we designed a vision chip utilizing CDS (correlated double sampling) technique. This vision chip could be used at the input stage for actual applications such as target tracking, fingerprint recognition and human-friendly robots, since it is robust to device mismatches.
{"title":"A biologically-motivated CMOS vision chip for edge detection robust to device mismatches","authors":"Jang-Kyoo Shin, Jong-Ho Park, Jung-Hwan Kim, Minho Lee","doi":"10.1109/SMELEC.2002.1217881","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217881","url":null,"abstract":"Human retina is able to detect the edge of the object by effective mechanism. We designed a CMOS vision chip by modeling retinal cells involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip. The vision chip detecting edge information from input image is used for input stage of vision systems. Therefore, the output offset affects the efficiency of entire vision system. In order to eliminate the output offset, we designed a vision chip utilizing CDS (correlated double sampling) technique. This vision chip could be used at the input stage for actual applications such as target tracking, fingerprint recognition and human-friendly robots, since it is robust to device mismatches.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128062348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217847
H. Younan, C. Eddy, S. Redkar
In this paper, a case of discolored bondpad is discussed. Failure analysis results showed the discoloration of bondpads was due to pinholes and Si dust around the pinholes. which were introduced during the wafer die sawing process caused by galvanic corrosion. Failure mechanism and characteristics of galvanic corrosion on Aluminium bondpads have been studied in this paper.
{"title":"Investigation and elimination of discolored bondpads on microchip","authors":"H. Younan, C. Eddy, S. Redkar","doi":"10.1109/SMELEC.2002.1217847","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217847","url":null,"abstract":"In this paper, a case of discolored bondpad is discussed. Failure analysis results showed the discoloration of bondpads was due to pinholes and Si dust around the pinholes. which were introduced during the wafer die sawing process caused by galvanic corrosion. Failure mechanism and characteristics of galvanic corrosion on Aluminium bondpads have been studied in this paper.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124826784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217885
L. Ali, R. Sidek, I. Aris, M.A.M. Ali, B.S. Suparjo
A new era began in microelectronics with the advent of integrated circuit (IC) technology. With dramatic improvement of integration technology, the complexities of IC testing has increased and become much more acute. Fault simulation technique for maximization of fault detection in IC testing is presented in this paper. Experiments on ISCAS bench-mark circuits has been conducted and it has been shown that quality test pattern can be generated using proper seed for the pattern generator, which can significantly improve fault coverage and reduce the time in testing IC.
{"title":"Maximization of fault detection in IC testing","authors":"L. Ali, R. Sidek, I. Aris, M.A.M. Ali, B.S. Suparjo","doi":"10.1109/SMELEC.2002.1217885","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217885","url":null,"abstract":"A new era began in microelectronics with the advent of integrated circuit (IC) technology. With dramatic improvement of integration technology, the complexities of IC testing has increased and become much more acute. Fault simulation technique for maximization of fault detection in IC testing is presented in this paper. Experiments on ISCAS bench-mark circuits has been conducted and it has been shown that quality test pattern can be generated using proper seed for the pattern generator, which can significantly improve fault coverage and reduce the time in testing IC.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129507086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217857
M. Harun, M. Othman
This paper presents the design of IC chips for smart card application. It consists of six modules, which is program counter, memory, register, transmitter, controller and Topspin. The VHDL code has been written and successfully stimulated and synthesized using Altera Max Plus II and Synopsis FPGA. The chip will transmit the data from the memory to the serial format. This is the simplex operation of smart cards.
本文介绍了一种用于智能卡应用的IC芯片的设计。它由程序计数器、存储器、寄存器、变送器、控制器和陀螺六个模块组成。编写了VHDL代码，并使用Altera Max Plus II和synosis FPGA成功地进行了仿真和合成。芯片将数据从存储器传输到串行格式。这是智能卡的简单操作。
{"title":"The design, simulation and synthesis of simplex IC microchips for smart card applications","authors":"M. Harun, M. Othman","doi":"10.1109/SMELEC.2002.1217857","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217857","url":null,"abstract":"This paper presents the design of IC chips for smart card application. It consists of six modules, which is program counter, memory, register, transmitter, controller and Topspin. The VHDL code has been written and successfully stimulated and synthesized using Altera Max Plus II and Synopsis FPGA. The chip will transmit the data from the memory to the serial format. This is the simplex operation of smart cards.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217878
M. M. Noor, B. Bais, B. Y. Majlis
The characterization of the KOH aqueous solution was done in order to study the effects of temperature and KOH concentration on the silicon etching rate for membrane formation. The study was done for temperatures ranging from 65/spl deg/C to 80/spl deg/C and KOH concentration ranging from 15% to 55%. Experiments showed that the temperature of 80/spl deg/C and KOH concentration of 35% will yield the optimum etching rate with the minimum surface roughness. A silicon membrane of thickness 48 /spl mu/m was produced with KOH concentration of 35% at the temperature of 75/spl deg/C for 7 hours and 45 minutes and the etching profile analyzed.
{"title":"The effects of temperature and KOH concentration on silicon etching rate and membrane surface roughness","authors":"M. M. Noor, B. Bais, B. Y. Majlis","doi":"10.1109/SMELEC.2002.1217878","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217878","url":null,"abstract":"The characterization of the KOH aqueous solution was done in order to study the effects of temperature and KOH concentration on the silicon etching rate for membrane formation. The study was done for temperatures ranging from 65/spl deg/C to 80/spl deg/C and KOH concentration ranging from 15% to 55%. Experiments showed that the temperature of 80/spl deg/C and KOH concentration of 35% will yield the optimum etching rate with the minimum surface roughness. A silicon membrane of thickness 48 /spl mu/m was produced with KOH concentration of 35% at the temperature of 75/spl deg/C for 7 hours and 45 minutes and the etching profile analyzed.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134485308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217859
Lakshmanan, M. Othman, M.A.M. Ali
This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix/spl I.bar/4 modified Booth algorithm and the Wallace Tree structure. The design is structured for a n/spl times/m multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2. To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModelSim3.4 CAD tools.
{"title":"High performance parallel multiplier using Wallace-Booth algorithm","authors":"Lakshmanan, M. Othman, M.A.M. Ali","doi":"10.1109/SMELEC.2002.1217859","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217859","url":null,"abstract":"This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix/spl I.bar/4 modified Booth algorithm and the Wallace Tree structure. The design is structured for a n/spl times/m multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2. To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModelSim3.4 CAD tools.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130769113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)
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