ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)最新文献
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217876
Dee Chang Fu, M.S. Jusoh, A. Mat, B. Y. Majlis
The molecular beam epitaxial growth of Si-doped GaAs, GaAs buffer layer, Al/sub 0.3/Ga/sub 0.7/As (x=0.3) and In/sub x/Ga/sub 1-x/As (x=0.2-0.4) on GaAs(100) substrate were examined by X-ray diffraction. Crystallinity of each layer was compared for each sample. The x composition value calculated from the In flux for InGaAs layers were compared to value obtained from X-ray diffraction matching to the Vegard Law/Fournet model curves to obtain the lattice parameters.
{"title":"XRD characterization of the MBE grown Si:GaAs, GaAs, AlGaAs, and InGaAs epilayer","authors":"Dee Chang Fu, M.S. Jusoh, A. Mat, B. Y. Majlis","doi":"10.1109/SMELEC.2002.1217876","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217876","url":null,"abstract":"The molecular beam epitaxial growth of Si-doped GaAs, GaAs buffer layer, Al/sub 0.3/Ga/sub 0.7/As (x=0.3) and In/sub x/Ga/sub 1-x/As (x=0.2-0.4) on GaAs(100) substrate were examined by X-ray diffraction. Crystallinity of each layer was compared for each sample. The x composition value calculated from the In flux for InGaAs layers were compared to value obtained from X-ray diffraction matching to the Vegard Law/Fournet model curves to obtain the lattice parameters.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116676379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217799
L. Tan, Peng Chen, S. Chua
The impact of growth regime on surface morphology, crystalline structural and electrical properties of n-type GaN using metalorganic chemical-vapor deposition (MOCVD), with intentional Si doping (SiH/sub 4/, 50.0 ppm) levels ranging from 2.5 sccm to 22.0 sccm (electron concentration varying from 1.46/spl times/10/sup 17/ to 1.07/spl times/10/sup 19/ cm/sup -3/) and V/III flux ratio from 1250 to 2800 (i.e. from Ga-rich regime to N-rich regime), are investigated. It has been found out that the V/III flux ratio affects the incorporation of Ga and N atoms into the film, and the screw dislocation generation. As for Si-incorporation, it increases the surface roughness and changes the edge dislocation generation. In this experiment, it shows clearly that those samples with V/III flux ratio of /spl sim/1500 which is close to the equilibrium condition exhibit the best properties.
{"title":"Impact of V/III flux ratio and Si-doping concentration on GaN grown by metalorganic chemical-vapor deposition on sapphire substrate","authors":"L. Tan, Peng Chen, S. Chua","doi":"10.1109/SMELEC.2002.1217799","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217799","url":null,"abstract":"The impact of growth regime on surface morphology, crystalline structural and electrical properties of n-type GaN using metalorganic chemical-vapor deposition (MOCVD), with intentional Si doping (SiH/sub 4/, 50.0 ppm) levels ranging from 2.5 sccm to 22.0 sccm (electron concentration varying from 1.46/spl times/10/sup 17/ to 1.07/spl times/10/sup 19/ cm/sup -3/) and V/III flux ratio from 1250 to 2800 (i.e. from Ga-rich regime to N-rich regime), are investigated. It has been found out that the V/III flux ratio affects the incorporation of Ga and N atoms into the film, and the screw dislocation generation. As for Si-incorporation, it increases the surface roughness and changes the edge dislocation generation. In this experiment, it shows clearly that those samples with V/III flux ratio of /spl sim/1500 which is close to the equilibrium condition exhibit the best properties.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116952574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217813
I. Hamammu, K. Ibrahim
Edge shunts are among the main factors causing reduction in solar cell open circuit voltage that is why their isolation is one of the main steps in solar cell manufacturing. Many techniques have been employed to achieve this goal, e.g. plasma etching, grinding, wet etching, etc. Unfortunately, these methods have the disadvantages of being very expensive, single cell process and consume a lot of dangerous chemicals. This work introduces a simple technique for edge shunt isolation, by making a mechanical grove through the emitter and uses it as back contact. It was found that with this technique the solar cell open circuit voltage can be increased by an amount up to 200 mV. This technique is simple, cheap and environmentally friendly in the sense that it uses no chemicals.
{"title":"Solar cell edge shunt isolation: a simplified approach","authors":"I. Hamammu, K. Ibrahim","doi":"10.1109/SMELEC.2002.1217813","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217813","url":null,"abstract":"Edge shunts are among the main factors causing reduction in solar cell open circuit voltage that is why their isolation is one of the main steps in solar cell manufacturing. Many techniques have been employed to achieve this goal, e.g. plasma etching, grinding, wet etching, etc. Unfortunately, these methods have the disadvantages of being very expensive, single cell process and consume a lot of dangerous chemicals. This work introduces a simple technique for edge shunt isolation, by making a mechanical grove through the emitter and uses it as back contact. It was found that with this technique the solar cell open circuit voltage can be increased by an amount up to 200 mV. This technique is simple, cheap and environmentally friendly in the sense that it uses no chemicals.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117148780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217845
Khairurrijal, F. A. Noor, Sukirno
An analytic model of the stress-induced leakage current in thin gate oxides was developed under the assumptions that traps created in the gate oxide during high field injection of electrons have an exponential distribution in energy and transport of the electrons localized in the traps is due to an activated process of motion from one trap to another. The electric field and temperature dependence of the leakage current in a wide range were explained successfully by the model.
{"title":"Modeling of stress-induced leakage current in thin gate oxides","authors":"Khairurrijal, F. A. Noor, Sukirno","doi":"10.1109/SMELEC.2002.1217845","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217845","url":null,"abstract":"An analytic model of the stress-induced leakage current in thin gate oxides was developed under the assumptions that traps created in the gate oxide during high field injection of electrons have an exponential distribution in energy and transport of the electrons localized in the traps is due to an activated process of motion from one trap to another. The electric field and temperature dependence of the leakage current in a wide range were explained successfully by the model.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217807
M. Reaz, M.S. Islam, M. Sulaiman
A pipeline floating point arithmetic logic unit (ALU) design using VHDL is introduced. The novelty of the ALU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple instruction executions are overlapped. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point ALU. Each module is divided into smaller modules. Two bits selection determines which operation takes place at a particular time. The pipeline modules are independent of each other. All the modules in the ALU design are realized using VHDL. Design functionalities are validated through simulation and compilation. Test vectors are created to verify the outputs as opposed to the calculated results. Besides verifying the outputs, the outputs' timing diagram and interfacing signals are also tracked to ensure that they adhere to the design specifications. Successful implementation of pipelining in floating point ALU using VHDL fulfills the needs for different high-performance applications.
{"title":"Pipeline floating point ALU design using VHDL","authors":"M. Reaz, M.S. Islam, M. Sulaiman","doi":"10.1109/SMELEC.2002.1217807","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217807","url":null,"abstract":"A pipeline floating point arithmetic logic unit (ALU) design using VHDL is introduced. The novelty of the ALU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple instruction executions are overlapped. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point ALU. Each module is divided into smaller modules. Two bits selection determines which operation takes place at a particular time. The pipeline modules are independent of each other. All the modules in the ALU design are realized using VHDL. Design functionalities are validated through simulation and compilation. Test vectors are created to verify the outputs as opposed to the calculated results. Besides verifying the outputs, the outputs' timing diagram and interfacing signals are also tracked to ensure that they adhere to the design specifications. Successful implementation of pipelining in floating point ALU using VHDL fulfills the needs for different high-performance applications.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217867
N. Yunus, R. Wagiran, V. Postoyalko
PIN diode microwave switch is designed using microwave harmonica and fabricated using PIN diode MA 47110, and realized on the microstrip. The switch is called single pole double throw, SPDT, switch and operating at 4 GHz.
{"title":"Design of a microstrip SPDT PIN diode switch","authors":"N. Yunus, R. Wagiran, V. Postoyalko","doi":"10.1109/SMELEC.2002.1217867","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217867","url":null,"abstract":"PIN diode microwave switch is designed using microwave harmonica and fabricated using PIN diode MA 47110, and realized on the microstrip. The switch is called single pole double throw, SPDT, switch and operating at 4 GHz.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124537772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217818
J. Lee, W. Choi, B. Choi, Y. Choi, D. Woo, Byung-Gook Park
30 nm nMOSFETs were fabricated on bulk-Si by processes for nanotechnology: the sidewall patterning technique, the RTO process and As/sub 2//sup +/ low energy implantation. With the aid of the sidewall patterning technique, very fine line patterns could be made accurately, uniformly and reproducibly all over the wafer. The RTO process made it possible to realize very thin oxide uniformly all over the wafer. As/sub 2//sup +/ implantation realized 12 nm shallow n/sup +/-p junctions. Based on these processes, 30 nm nMOSFETs were realized and their electrical characteristics were analyzed. They were 30 nm in channel length, 9 ? in channel width and 1 nm in gate oxide thickness. Their threshold voltage was 230 mV. They had drive current of 360 ?/? and maximum intrinsic transconductance of 700 mS/mm at 1.0 V. Also, DIBL was 250 mV/V and subthreshold slope was 110 mV/dec. The 30 nm nMOSFET showed normal transistor operations in 30 nm regime with the planar structure on bulk Si.
{"title":"30 nm MOSFET development based on processes for nanotechnology","authors":"J. Lee, W. Choi, B. Choi, Y. Choi, D. Woo, Byung-Gook Park","doi":"10.1109/SMELEC.2002.1217818","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217818","url":null,"abstract":"30 nm nMOSFETs were fabricated on bulk-Si by processes for nanotechnology: the sidewall patterning technique, the RTO process and As/sub 2//sup +/ low energy implantation. With the aid of the sidewall patterning technique, very fine line patterns could be made accurately, uniformly and reproducibly all over the wafer. The RTO process made it possible to realize very thin oxide uniformly all over the wafer. As/sub 2//sup +/ implantation realized 12 nm shallow n/sup +/-p junctions. Based on these processes, 30 nm nMOSFETs were realized and their electrical characteristics were analyzed. They were 30 nm in channel length, 9 ? in channel width and 1 nm in gate oxide thickness. Their threshold voltage was 230 mV. They had drive current of 360 ?/? and maximum intrinsic transconductance of 700 mS/mm at 1.0 V. Also, DIBL was 250 mV/V and subthreshold slope was 110 mV/dec. The 30 nm nMOSFET showed normal transistor operations in 30 nm regime with the planar structure on bulk Si.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217809
K. Linggajaya, D. M. Anh, M. J. Guo, Y. K. Seng
Passive polyphase filter and first order active polyphase filter building blocks have been commonly used in the image reject downconverter. However, to operate in a wideband system and to achieve sufficient image rejection, the filter requires a cascade of multiple building blocks, which leads to high signal loss, noise and power consumption. This paper describes a second order polyphase filter building block and its implementation in the image reject downconverter. The transfer function of the proposed filter is obtained by applying a frequency translation, converting a second order low pass filter to an asymmetrical bandpass filter. This bandpass characteristic eliminates the need for low pass filter when it is implemented in the image reject downconverter. Unlike the passive polyphase filter, the proposed circuit may provide gain to the signal. Furthermore, it requires fewer stages of building blocks to operate in the same bandwidth and the same image reject ratio compared to existing polyphase filter building block. This paper reports the performance of an image reject downconverter using a fifth order polyphase filter circuit built from the combination of a first order filter and two second order filters. The circuit, implemented in 0.18 /spl mu/m CMOS technology, is designed to downconvert a 60 MHz bandwidth RF signal centred around 1.8 GHz to IF signal centred at 70 MHz while rejecting the mirror image signal appearing around 1.66 GHz. The polyphase filter gives more than 60 dB image rejection while consuming 8.272 mA from a 2.5 power supply.
{"title":"A new active polyphase filter for wideband image reject downconverter","authors":"K. Linggajaya, D. M. Anh, M. J. Guo, Y. K. Seng","doi":"10.1109/SMELEC.2002.1217809","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217809","url":null,"abstract":"Passive polyphase filter and first order active polyphase filter building blocks have been commonly used in the image reject downconverter. However, to operate in a wideband system and to achieve sufficient image rejection, the filter requires a cascade of multiple building blocks, which leads to high signal loss, noise and power consumption. This paper describes a second order polyphase filter building block and its implementation in the image reject downconverter. The transfer function of the proposed filter is obtained by applying a frequency translation, converting a second order low pass filter to an asymmetrical bandpass filter. This bandpass characteristic eliminates the need for low pass filter when it is implemented in the image reject downconverter. Unlike the passive polyphase filter, the proposed circuit may provide gain to the signal. Furthermore, it requires fewer stages of building blocks to operate in the same bandwidth and the same image reject ratio compared to existing polyphase filter building block. This paper reports the performance of an image reject downconverter using a fifth order polyphase filter circuit built from the combination of a first order filter and two second order filters. The circuit, implemented in 0.18 /spl mu/m CMOS technology, is designed to downconvert a 60 MHz bandwidth RF signal centred around 1.8 GHz to IF signal centred at 70 MHz while rejecting the mirror image signal appearing around 1.66 GHz. The polyphase filter gives more than 60 dB image rejection while consuming 8.272 mA from a 2.5 power supply.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130689344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217816
E. Xiao, J. Yuan, Hong Yang
RF circuit performance degradations due to hot carrier (HC) and soft breakdown (SBD) effects are studied with 0.16 /spl mu/m CMOS technology. Two design techniques are proposed to reduce the HC and SBD effects on RF circuits. A low noise amplifier (LNA) and a voltage-controlled oscillator (VCO) are used to verify the design techniques that can be used to build more reliable RF circuits.
{"title":"Hot carrier and soft breakdown reliability for RF circuits","authors":"E. Xiao, J. Yuan, Hong Yang","doi":"10.1109/SMELEC.2002.1217816","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217816","url":null,"abstract":"RF circuit performance degradations due to hot carrier (HC) and soft breakdown (SBD) effects are studied with 0.16 /spl mu/m CMOS technology. Two design techniques are proposed to reduce the HC and SBD effects on RF circuits. A low noise amplifier (LNA) and a voltage-controlled oscillator (VCO) are used to verify the design techniques that can be used to build more reliable RF circuits.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217863
M.S.A. Rahman, S. Shaari
Phosphorous doped silica layers are grown from tetraethylorthosilicate (TEOS), phosphoric acid and PBF polymer, with spin coating technique on silica glass. The phosphorus-doped and boron-codoped photosensitive silica waveguide samples show index modulation around 1/spl times/10/sup -4/ for thickness between 3 /spl mu/m to 8 /spl mu/m. The refractive index range is between 1.51 to 1.54 which is dependent on the coating parameters and concentration of phosphoric acid. Photosensitivity test and treatment are performed using a 366 nm UV source, with 0.36 mW/cm/sup 2/ power at pulse rate of 50 Hz. All samples show a decrease in refractive indices under the UV exposure. They begin to saturate after first 30-60 minutes in treatment. Further UV exposure will slowly increase again the refractive index. It is estimated that, with a laser source power from ArF and KrF of about 10 mW, the Bragg grating writing duration will be in between 20 to 30 second. The samples were also thermally treated to increase the index modulation by the factor of 10.
{"title":"Photosensitive phosphorus-doped boron-codoped silica planar waveguide for waveguide Bragg grating prepared by spin coating","authors":"M.S.A. Rahman, S. Shaari","doi":"10.1109/SMELEC.2002.1217863","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217863","url":null,"abstract":"Phosphorous doped silica layers are grown from tetraethylorthosilicate (TEOS), phosphoric acid and PBF polymer, with spin coating technique on silica glass. The phosphorus-doped and boron-codoped photosensitive silica waveguide samples show index modulation around 1/spl times/10/sup -4/ for thickness between 3 /spl mu/m to 8 /spl mu/m. The refractive index range is between 1.51 to 1.54 which is dependent on the coating parameters and concentration of phosphoric acid. Photosensitivity test and treatment are performed using a 366 nm UV source, with 0.36 mW/cm/sup 2/ power at pulse rate of 50 Hz. All samples show a decrease in refractive indices under the UV exposure. They begin to saturate after first 30-60 minutes in treatment. Further UV exposure will slowly increase again the refractive index. It is estimated that, with a laser source power from ArF and KrF of about 10 mW, the Bragg grating writing duration will be in between 20 to 30 second. The samples were also thermally treated to increase the index modulation by the factor of 10.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133987716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)
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