Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626904
J. Fitt, J. Gondek, Zygmunt Parzelka, W. Zaraska
The paper presents the design and technology of production of thick-film intelligent sensors (TF-ASIC), their characteristics and applications. The novel hybrid sensors and application specific integrated sensors were made with the use of high technology materials manufactured by Du Pont Nemours Co. (USA) and ESL (USA). The authors also discuss the prospects of industrial and other applications of such sensors.
{"title":"Thick-film intelligent sensors using new Du Pont and ESL high technology materials","authors":"J. Fitt, J. Gondek, Zygmunt Parzelka, W. Zaraska","doi":"10.1109/IEMT.1997.626904","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626904","url":null,"abstract":"The paper presents the design and technology of production of thick-film intelligent sensors (TF-ASIC), their characteristics and applications. The novel hybrid sensors and application specific integrated sensors were made with the use of high technology materials manufactured by Du Pont Nemours Co. (USA) and ESL (USA). The authors also discuss the prospects of industrial and other applications of such sensors.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115877621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626936
R. Kubin, V. Ho
As the use of solder flip chip devices increases, it is important to ensure that the design and materials used in the die to solder bump structure are compatible with one another and provide a robust system that will meet reliability requirements. The key elements of this system are the final metal pad design, die passivation, and under bump metallization. This paper examines the interactions of these elements and offers some recommendations based on experimental observations.
{"title":"Silicon device pad design considerations for solder flip chip applications","authors":"R. Kubin, V. Ho","doi":"10.1109/IEMT.1997.626936","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626936","url":null,"abstract":"As the use of solder flip chip devices increases, it is important to ensure that the design and materials used in the die to solder bump structure are compatible with one another and provide a robust system that will meet reliability requirements. The key elements of this system are the final metal pad design, die passivation, and under bump metallization. This paper examines the interactions of these elements and offers some recommendations based on experimental observations.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121329025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626948
Z. Celik, D. Copeland, A. Mertol
Increasing power requirements for Plastic Ball Grid Array (PBGA) packages demand better thermal management for increased performance and reliability. One of the important parameters that affect the rate of thermal dissipation is the thermal resistance between the package surface and the heat sink. An Enhanced PBGA package of 40 mm /spl times/40 mm body size with an Intricast plate fin heat sink was used to evaluate commercially available interface materials. Junction-to-ambient resistance of the package and the base temperature at the center of the heat sink was measured with respect to air velocity. Thermal cycling was carried out to determine the long term effects on the the thermal performance. In addition to experiments, a computational model was also used. Relative performance of interface materials was determined.
{"title":"Thermal enhancement and reliability of 40 mm EPBGA packages with interface materials","authors":"Z. Celik, D. Copeland, A. Mertol","doi":"10.1109/IEMT.1997.626948","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626948","url":null,"abstract":"Increasing power requirements for Plastic Ball Grid Array (PBGA) packages demand better thermal management for increased performance and reliability. One of the important parameters that affect the rate of thermal dissipation is the thermal resistance between the package surface and the heat sink. An Enhanced PBGA package of 40 mm /spl times/40 mm body size with an Intricast plate fin heat sink was used to evaluate commercially available interface materials. Junction-to-ambient resistance of the package and the base temperature at the center of the heat sink was measured with respect to air velocity. Thermal cycling was carried out to determine the long term effects on the the thermal performance. In addition to experiments, a computational model was also used. Relative performance of interface materials was determined.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626891
A. Sinni, M. A. Palmer
Flux residue has been a manufacturing concern for many decades, as these potentially conductive residues increase the possibility of circuit failure. To avoid this, printed wire assemblies were cleaned with chloroflourocarbon (CFC) solvents. However, CFC's are very detrimental to the environment, contributing to the destruction of the ozone layer. While it is possible to identify an environmentally friendly cleaner, eliminating residue formation, and thus the need for any cleaning is also desirable. A series of studies conducted at Rensselaer demonstrated that residue forms as a result of a reaction between either the retained flux or the by-product of the fluxing reaction, and water vapor. This study evaluates the growth of residue and residue precursor (flux or by-product) in order to determine the chemical kinetics of residue formation and the relation to the soldering flux.
{"title":"Kinetics of flux residue formation in a humid environment","authors":"A. Sinni, M. A. Palmer","doi":"10.1109/IEMT.1997.626891","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626891","url":null,"abstract":"Flux residue has been a manufacturing concern for many decades, as these potentially conductive residues increase the possibility of circuit failure. To avoid this, printed wire assemblies were cleaned with chloroflourocarbon (CFC) solvents. However, CFC's are very detrimental to the environment, contributing to the destruction of the ozone layer. While it is possible to identify an environmentally friendly cleaner, eliminating residue formation, and thus the need for any cleaning is also desirable. A series of studies conducted at Rensselaer demonstrated that residue forms as a result of a reaction between either the retained flux or the by-product of the fluxing reaction, and water vapor. This study evaluates the growth of residue and residue precursor (flux or by-product) in order to determine the chemical kinetics of residue formation and the relation to the soldering flux.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626867
M. Kasem
This paper briefly illustrates the principles of Integrated Product Development (IPD) as an effective framework for new product development. However, the success of management implementing IPD is dependent on a number of fundamental changes in the current development process. These include emphasis on teamwork and the expansion of the role of manufacturing, as well as the application of Design for Manufacturability (DFM) as a business driver. The paper also describes the superior characteristics of 8-lead power TSSOP packages, which were developed for ultra high density Trench MOSFETs using IPD principles.
{"title":"Integrated development and manufacturing methodology for advanced power MOSFETs","authors":"M. Kasem","doi":"10.1109/IEMT.1997.626867","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626867","url":null,"abstract":"This paper briefly illustrates the principles of Integrated Product Development (IPD) as an effective framework for new product development. However, the success of management implementing IPD is dependent on a number of fundamental changes in the current development process. These include emphasis on teamwork and the expansion of the role of manufacturing, as well as the application of Design for Manufacturability (DFM) as a business driver. The paper also describes the superior characteristics of 8-lead power TSSOP packages, which were developed for ultra high density Trench MOSFETs using IPD principles.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130256863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626930
J. Partridge, C. Hart, P. Boysan, B. Surratt, R. Foehringer
Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.
具有1.27毫米间距阵列的球栅阵列(BGA)封装现在正在扩展到细间距BGA，或者具有球直径0.3毫米和阵列间距小至0.5毫米的芯片级封装(CSP)。目前的工作分析了将这些封装集成到大批量SMT装配线中的影响，并检查了工艺和板变量对整个装配可靠性的影响。目前研究选择的CSP是0.75 mm间距的CSP，计划取代目前用于大容量，小尺寸闪存产品的0.5 mm引线间距薄小轮廓封装(TSOP)。CSP尺寸约为5.6 mm × 7.4 mm，与传统的TSOP相比，封装面积减少了80%，占地面积为12 mm × 20 mm。该研究考察了锡膏印刷参数、纯焊剂组装和印刷电路板表面处理(如浸金和焊料流平)的影响。在构建过程中，使用在线自动激光扫描轮廓仪对2800多个单独的CSP焊盘进行了锡膏体积测量。可靠性测试车辆使用csp、tsop和其他表面贴装组件组装，然后进行从0/spl°C到100/spl°C、40/spl°C到85/spl°C的加速热循环测试。使用优化的高速芯片放置器放置CSP，以高达每秒5个零件的速率放置CSP。经过四个月的测试后，给出了中期可靠性测试结果，并讨论了TSOP与MicroBGA封装结构。
{"title":"High reliability assembly of chip scale packages","authors":"J. Partridge, C. Hart, P. Boysan, B. Surratt, R. Foehringer","doi":"10.1109/IEMT.1997.626930","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626930","url":null,"abstract":"Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127606541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626890
H. Zhang, T. Kuo
Disassembly sequence planning is an essential issue for end-of-life (EOL) product recycling. Wide diffusion of consumer goods and shortening of product life-cycle have caused an increasing quantity of used products being discarded. The most evident effect is that landfill capacity is being used up. This revolves that a systematic technology in recycling is imperative. This paper developed a graph based heuristic approach for the product recycling. The model is embedded on a graph representation which is obtained by generating disassembly sequences. With graph representation, the problem of identifying the disassembly sequence planning is transformed into a graph search problem. By solving the graph search problem, one can determine the termination of disassembly and generate the disassembly sequence. The disposition of end-of-life product is becoming very important issues recently. The proposed graph-based approach is to find the feasible disassembly sequences from the CAD system directly and automatically. The benefit is to provide some useful information for the designer to evaluate the disassembly problem during the design stage.
{"title":"A graph-based disassembly sequence planning for EOL product recycling","authors":"H. Zhang, T. Kuo","doi":"10.1109/IEMT.1997.626890","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626890","url":null,"abstract":"Disassembly sequence planning is an essential issue for end-of-life (EOL) product recycling. Wide diffusion of consumer goods and shortening of product life-cycle have caused an increasing quantity of used products being discarded. The most evident effect is that landfill capacity is being used up. This revolves that a systematic technology in recycling is imperative. This paper developed a graph based heuristic approach for the product recycling. The model is embedded on a graph representation which is obtained by generating disassembly sequences. With graph representation, the problem of identifying the disassembly sequence planning is transformed into a graph search problem. By solving the graph search problem, one can determine the termination of disassembly and generate the disassembly sequence. The disposition of end-of-life product is becoming very important issues recently. The proposed graph-based approach is to find the feasible disassembly sequences from the CAD system directly and automatically. The benefit is to provide some useful information for the designer to evaluate the disassembly problem during the design stage.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125630881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626945
C. Edwards, P. Nguyen, J. Kennedy
Today's leading-edge integrated circuits are driven by higher performance requirements, including faster operating speeds and enhanced power dissipation. These requirements create a need for thermal management. To address this need, cyanate ester (CE) based materials, commonly used in semiconductor die attach applications, can now be used to attach heat slugs to laminate packages. While other technologies, including epoxy films and solders remain viable alternatives, CE pastes provide several process advantages such as long pot life, quick-cure capability and improved process flexibility.
{"title":"Heat slug attach: a cyanate ester based solution","authors":"C. Edwards, P. Nguyen, J. Kennedy","doi":"10.1109/IEMT.1997.626945","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626945","url":null,"abstract":"Today's leading-edge integrated circuits are driven by higher performance requirements, including faster operating speeds and enhanced power dissipation. These requirements create a need for thermal management. To address this need, cyanate ester (CE) based materials, commonly used in semiconductor die attach applications, can now be used to attach heat slugs to laminate packages. While other technologies, including epoxy films and solders remain viable alternatives, CE pastes provide several process advantages such as long pot life, quick-cure capability and improved process flexibility.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133842403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626966
Z. Mei, F. Hua, J. Glazer, C. Key
Low temperature soldering may reduce the cost for surface mount electronic assembly by using low cost electronic components and substrate materials. It also provides options for step soldering, and reduces the risk of thermally induced damages. A vast amount of Sn-Pb-Bi-In alloys are available for any given melting temperature (liquidus) between 50/spl deg/C and 183/spl deg/C. Currently available water clean or no-clean fluxes, however, are not suitable for low temperature soldering, because they are activated at temperature higher than 150/spl deg/C. Two solderability test methods were used to evaluate the newly developed fluxes for low temperature soldering: (a) spreading test to compare the relative strength of the fluxes, and (b) wetting balance to determine the activation temperature of the fluxes. The mechanical properties (shear strength, creep, isothermal and thermal fatigue) of several common low temperature solders were determined. Prototypes of PCBs assembled with several low temperature solders were successfully built and passed typical product qualification tests. Potential problems for low temperature soldering are the poor adhesion strength of the low temperature solders to Alloy 42 leaded components, and exceptional grain growth and early thermal failure when 58Bi-42Sn was used to solder on Sn-Pb surface.
{"title":"Low temperature soldering","authors":"Z. Mei, F. Hua, J. Glazer, C. Key","doi":"10.1109/IEMT.1997.626966","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626966","url":null,"abstract":"Low temperature soldering may reduce the cost for surface mount electronic assembly by using low cost electronic components and substrate materials. It also provides options for step soldering, and reduces the risk of thermally induced damages. A vast amount of Sn-Pb-Bi-In alloys are available for any given melting temperature (liquidus) between 50/spl deg/C and 183/spl deg/C. Currently available water clean or no-clean fluxes, however, are not suitable for low temperature soldering, because they are activated at temperature higher than 150/spl deg/C. Two solderability test methods were used to evaluate the newly developed fluxes for low temperature soldering: (a) spreading test to compare the relative strength of the fluxes, and (b) wetting balance to determine the activation temperature of the fluxes. The mechanical properties (shear strength, creep, isothermal and thermal fatigue) of several common low temperature solders were determined. Prototypes of PCBs assembled with several low temperature solders were successfully built and passed typical product qualification tests. Potential problems for low temperature soldering are the poor adhesion strength of the low temperature solders to Alloy 42 leaded components, and exceptional grain growth and early thermal failure when 58Bi-42Sn was used to solder on Sn-Pb surface.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133933862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626953
R. Allison, J. Yu, L. Tsai, Chih-Ming Liu, M. Drummond, D. Kayton, T. Sustae, J. Witte
The representation of a factory-level capacity model and an enterprise-level model have traditionally been incompatible. The goal of this study is to resolve the incompatibility problem. Factory systems contain detailed data striving to accurately predict facility capabilities. Enterprise optimization systems prefer an aggregation of data, representing key bottleneck resources throughout a corporation. The focus on key resources reduces modeling complexity and subsequently reduces the problem solving cycle. This study attempts to build a bridge between the capabilities of a factory simulation-based capacity planning software tool, ManSim(R)/X, and an enterprise optimization system, TEOS/sup TM/ (TYECIN Enterprise Optimization System), both from TYECIN Systems Inc. The project involves studying the predecessor of TEOS (IMPReSS 2.0) at Harris Semiconductor in Findlay, Ohio.
工厂级容量模型的表示和企业级模型的表示传统上是不兼容的。本研究的目的是解决不相容问题。工厂系统包含详细的数据，力求准确地预测工厂的能力。企业优化系统更喜欢数据聚合，代表整个公司的关键瓶颈资源。对关键资源的关注减少了建模的复杂性，并随后减少了问题解决周期。本研究试图在基于工厂模拟的产能规划软件工具ManSim(R)/X和企业优化系统TEOS/sup TM/ (TYECIN企业优化系统)之间建立一座桥梁，两者都来自TYECIN Systems Inc.。该项目包括在俄亥俄州芬德雷的哈里斯半导体公司研究TEOS的前身(IMPReSS 2.0)。
{"title":"Macro model development as a bridge between factory level simulation and LP enterprise systems","authors":"R. Allison, J. Yu, L. Tsai, Chih-Ming Liu, M. Drummond, D. Kayton, T. Sustae, J. Witte","doi":"10.1109/IEMT.1997.626953","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626953","url":null,"abstract":"The representation of a factory-level capacity model and an enterprise-level model have traditionally been incompatible. The goal of this study is to resolve the incompatibility problem. Factory systems contain detailed data striving to accurately predict facility capabilities. Enterprise optimization systems prefer an aggregation of data, representing key bottleneck resources throughout a corporation. The focus on key resources reduces modeling complexity and subsequently reduces the problem solving cycle. This study attempts to build a bridge between the capabilities of a factory simulation-based capacity planning software tool, ManSim(R)/X, and an enterprise optimization system, TEOS/sup TM/ (TYECIN Enterprise Optimization System), both from TYECIN Systems Inc. The project involves studying the predecessor of TEOS (IMPReSS 2.0) at Harris Semiconductor in Findlay, Ohio.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115426889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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