Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626951
S. Wood
The objective of this work is to provide insight into the sources and magnitude of the costs that result from lost market responsiveness due to long capacity lead times. A model has been developed to determine the impact of tool lead times on the expected present value of monolithic fabs and modular a fab over the fab lifetime. The model makes the following assumptions and approximations: Demand follows a random walk characterized by a known drift rate and volatility; Capacity lead times are known in advance longer capacity lead times result in tools being ordered earlier than tools with late lead times; Management has the option of sparsely populating a fab initially and then adding additional tools as needed. This is referred to as a modular fab. Cost parameters representing modern 200 mm wafer fabs are used. Based on the above assumptions optimal capacity expansion schedules are numerically generated. Initial results show that as capacity lead times get shorter, initial fab size is likely to be smaller and future capacity additions are likely to become more frequent. If capacity lead times are short, fab capacities can be more accurately matched to demand, achieving higher expected revenues. The increase in revenues can be used to evaluate the financial value of shorter capacity lead times.
{"title":"The impact of tool delivery times on the optimal capacity and value of semiconductor wafer fabs","authors":"S. Wood","doi":"10.1109/IEMT.1997.626951","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626951","url":null,"abstract":"The objective of this work is to provide insight into the sources and magnitude of the costs that result from lost market responsiveness due to long capacity lead times. A model has been developed to determine the impact of tool lead times on the expected present value of monolithic fabs and modular a fab over the fab lifetime. The model makes the following assumptions and approximations: Demand follows a random walk characterized by a known drift rate and volatility; Capacity lead times are known in advance longer capacity lead times result in tools being ordered earlier than tools with late lead times; Management has the option of sparsely populating a fab initially and then adding additional tools as needed. This is referred to as a modular fab. Cost parameters representing modern 200 mm wafer fabs are used. Based on the above assumptions optimal capacity expansion schedules are numerically generated. Initial results show that as capacity lead times get shorter, initial fab size is likely to be smaller and future capacity additions are likely to become more frequent. If capacity lead times are short, fab capacities can be more accurately matched to demand, achieving higher expected revenues. The increase in revenues can be used to evaluate the financial value of shorter capacity lead times.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121247257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626934
H. Ezawa, M. Miyata, H. Inoue
A novel eutectic solder bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall bumps as plated using a new negative-type photoresist and eutectic solder electroplating provide several advantages over conventional mushroom bumps. The novel developed process gives the bump height uniformity as reflowed of less than 10% within the wafer. Composition measurements using ICP spectrometry have been performed to investigate the bump height dependence on solder compositions and the metal content dependence of a plating solution on the solder composition uniformity within the wafer. Experimental results show that the plating solution with the total metal concentration of more than 60 g/l gives a uniformity at eutectic point of less than 3% within wafer. In addition, we have confirmed that the use of a eutectic solder disk anode keeps the composition of a plating solution constant for a long term product run.
{"title":"Eutectic solder bump process for ULSI flip chip technology","authors":"H. Ezawa, M. Miyata, H. Inoue","doi":"10.1109/IEMT.1997.626934","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626934","url":null,"abstract":"A novel eutectic solder bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall bumps as plated using a new negative-type photoresist and eutectic solder electroplating provide several advantages over conventional mushroom bumps. The novel developed process gives the bump height uniformity as reflowed of less than 10% within the wafer. Composition measurements using ICP spectrometry have been performed to investigate the bump height dependence on solder compositions and the metal content dependence of a plating solution on the solder composition uniformity within the wafer. Experimental results show that the plating solution with the total metal concentration of more than 60 g/l gives a uniformity at eutectic point of less than 3% within wafer. In addition, we have confirmed that the use of a eutectic solder disk anode keeps the composition of a plating solution constant for a long term product run.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128515972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626922
A. Singer, J.F. Wzorek
The IC industry amounted to $140 billion worldwide in 1996. As the consumer and portable electronics portion of this market grows, so will. The demand for component packaging that meets higher density requirements. Chip scale packaging (CSP) addresses this need, but many technology variations exist, creating confusion among potential users about which technology may suit their application. Comparing alternative packaging technologies is a complex task, involving a prioritization of cost, performance, and business strategy issues. This paper focuses only one portion of the decision-making equation: cost. Using a tool for assessing the manufacturing cost of electronic packaging, IBIS has analyzed the cost outlook for several chip scale packaging technologies, including wafer-scale processing as well as individual component packaging. This paper examines the costs for both implementations, analyzing their cost sensitivity to product design variables (i.e., # of I/Os per IC and lead pitch) and manufacturing conditions (i.e., annual production volume and yield).
{"title":"Cost issues for chip scale packaging","authors":"A. Singer, J.F. Wzorek","doi":"10.1109/IEMT.1997.626922","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626922","url":null,"abstract":"The IC industry amounted to $140 billion worldwide in 1996. As the consumer and portable electronics portion of this market grows, so will. The demand for component packaging that meets higher density requirements. Chip scale packaging (CSP) addresses this need, but many technology variations exist, creating confusion among potential users about which technology may suit their application. Comparing alternative packaging technologies is a complex task, involving a prioritization of cost, performance, and business strategy issues. This paper focuses only one portion of the decision-making equation: cost. Using a tool for assessing the manufacturing cost of electronic packaging, IBIS has analyzed the cost outlook for several chip scale packaging technologies, including wafer-scale processing as well as individual component packaging. This paper examines the costs for both implementations, analyzing their cost sensitivity to product design variables (i.e., # of I/Os per IC and lead pitch) and manufacturing conditions (i.e., annual production volume and yield).","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116879831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626877
S. Venkateswaran, K. Srihari, J. Adriance, G. Westby
The goal of stencil printing solder paste in surface mount printed circuit board (PCB) assembly is to apply an accurate and repeatable volume of solder paste at precise locations. The causes for a substantial proportion of the problems associated with PCB assembly can be traced back to the solder paste printing process. Control of the stencil printing process has become significantly more important over the years due to the introduction of ultra fine pitch technologies. Three important issues have to be considered in the stencil printing process to obtain a good yield. They are: (i) setting up the process in an efficient way, (ii) monitoring and controlling the process when necessary and (iii) troubleshooting the process when a defect occurs. This research focused on the design and development of software systems that could perform the above-mentioned functions. Three systems were developed in the research discussed in this paper. They are the process advisor, the intelligent control system (or the ICS) and the diagnosis system. The process advisor (the first system) provides for the setup of the stencil printing process. It helps the user to set up a new as well as an existing application. The process advisor also helps the user in estimating the volume of solder paste that would be deposited for a given stencil thickness and aperture dimensions. The ICS (the second system) was developed to control the stencil printing process in real-time. The diagnosis system (the third system) is used to troubleshoot the process, if needed.
{"title":"A realtime process control system for solder paste stencil printing","authors":"S. Venkateswaran, K. Srihari, J. Adriance, G. Westby","doi":"10.1109/IEMT.1997.626877","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626877","url":null,"abstract":"The goal of stencil printing solder paste in surface mount printed circuit board (PCB) assembly is to apply an accurate and repeatable volume of solder paste at precise locations. The causes for a substantial proportion of the problems associated with PCB assembly can be traced back to the solder paste printing process. Control of the stencil printing process has become significantly more important over the years due to the introduction of ultra fine pitch technologies. Three important issues have to be considered in the stencil printing process to obtain a good yield. They are: (i) setting up the process in an efficient way, (ii) monitoring and controlling the process when necessary and (iii) troubleshooting the process when a defect occurs. This research focused on the design and development of software systems that could perform the above-mentioned functions. Three systems were developed in the research discussed in this paper. They are the process advisor, the intelligent control system (or the ICS) and the diagnosis system. The process advisor (the first system) provides for the setup of the stencil printing process. It helps the user to set up a new as well as an existing application. The process advisor also helps the user in estimating the volume of solder paste that would be deposited for a given stencil thickness and aperture dimensions. The ICS (the second system) was developed to control the stencil printing process in real-time. The diagnosis system (the third system) is used to troubleshoot the process, if needed.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116975212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626929
R. Roney
As die mount assembly begins to enter the high volume surface mount assembly mainstream and electronics designers and engineers begin serious discussions about converting surface mount designs to die mount assembly designs for the purposes of miniaturization or improved electrical performance, it is desirable to have a cost model which can be used to understand the cost implications. The cost for die mount assembly is impacted in three major categories: materials, assembly, and repair. In this paper, a cost model, addressing the assembly portion of the cost, is developed and partially verified. The cost model is based on a current surface mount assembly cost model and is intended to be used as a guideline for comparing the assembly cost of surface mount assemblies to the assembly cost for die mount assemblies.
{"title":"Cost considerations for integrating flip chip and chip on board technologies into high volume manufacturing areas","authors":"R. Roney","doi":"10.1109/IEMT.1997.626929","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626929","url":null,"abstract":"As die mount assembly begins to enter the high volume surface mount assembly mainstream and electronics designers and engineers begin serious discussions about converting surface mount designs to die mount assembly designs for the purposes of miniaturization or improved electrical performance, it is desirable to have a cost model which can be used to understand the cost implications. The cost for die mount assembly is impacted in three major categories: materials, assembly, and repair. In this paper, a cost model, addressing the assembly portion of the cost, is developed and partially verified. The cost model is based on a current surface mount assembly cost model and is intended to be used as a guideline for comparing the assembly cost of surface mount assemblies to the assembly cost for die mount assemblies.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121571212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626946
T. Thompson
The glob top BGA has been pursued by multiple companies to reduce package cost and cycle time. This report discusses material and process improvements that can be made to enhance the packages' performance to a JEDEC Level 3. The material evaluations included in this report tested different liquid encapsulants, die attach epoxies and solder resist materials. Process improvements targeted using different cure profiles for the encapsulants, cleaning processes and location of special cleaning in the assembly process. Flag designs that reduce Cu surface area on the substrate for possible better die attach adhesion are also discussed. These results are benchmarked with the overmolded plastic ball grid area (PBGA) performance which is a JEDEC Level 5. The reliability test response was C-SAM to inspect for delamination at various package interfaces and weight gain to determine package moisture absorption and deabsorption rates.
{"title":"Moisture absorption and autoclave performance optimization of glob top ball grid array","authors":"T. Thompson","doi":"10.1109/IEMT.1997.626946","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626946","url":null,"abstract":"The glob top BGA has been pursued by multiple companies to reduce package cost and cycle time. This report discusses material and process improvements that can be made to enhance the packages' performance to a JEDEC Level 3. The material evaluations included in this report tested different liquid encapsulants, die attach epoxies and solder resist materials. Process improvements targeted using different cure profiles for the encapsulants, cleaning processes and location of special cleaning in the assembly process. Flag designs that reduce Cu surface area on the substrate for possible better die attach adhesion are also discussed. These results are benchmarked with the overmolded plastic ball grid area (PBGA) performance which is a JEDEC Level 5. The reliability test response was C-SAM to inspect for delamination at various package interfaces and weight gain to determine package moisture absorption and deabsorption rates.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114305637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626921
L. Su, M. Louis, C. Reber
This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.
{"title":"Cost analysis of chip scale packaging","authors":"L. Su, M. Louis, C. Reber","doi":"10.1109/IEMT.1997.626921","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626921","url":null,"abstract":"This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122156208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626959
D. Bhogeswara Rao, M. Prakash
Shadow Moire technique was used to study the out-of-plane displacements that represent warpage of advanced Plastic Ball Grid Array (PBGA) packages. Two types of PBGA packages, die-up and cavity-down configurations, were studied. The latter type is usually known as Enhanced Plastic Ball Grid Array (EPBGA) package due to the advantage it offers for thermal dissipation. Shadow Moire studies indicated that cavity-down package substrates warp in a concave configuration. Die-up package substrates warp in a convex configuration. Increase in temperatures up to 240/spl deg/C had an insignificant effect on the warpage of cavity-down substrates, whereas the die-up package substrate warpage improved with increasing temperature. However, the die-up substrates reverted to their original warpage upon cooling. The sum of the warpage and the ball diameter variation account for almost all the non-planarity. The packages with worse coplanarities showed invariably worse warpages. Substrate warpage of 4 mils or less is required for the successful assembly of PBGA packages. Since cavity-down packages do not show any improvement with increasing temperature, package non-planarity should be less than 7 mils by the seating plane method to ensure less than 4 mils of warpage. The assembly processes can tolerate higher levels of coplanarity for die-up packages as warpage improves at reflow temperatures. It is recommended that the coplanarity be measured by the seating plane method.
{"title":"Effect of substrate warpage on the second level assembly of advanced plastic ball grid array (PBGA) packages","authors":"D. Bhogeswara Rao, M. Prakash","doi":"10.1109/IEMT.1997.626959","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626959","url":null,"abstract":"Shadow Moire technique was used to study the out-of-plane displacements that represent warpage of advanced Plastic Ball Grid Array (PBGA) packages. Two types of PBGA packages, die-up and cavity-down configurations, were studied. The latter type is usually known as Enhanced Plastic Ball Grid Array (EPBGA) package due to the advantage it offers for thermal dissipation. Shadow Moire studies indicated that cavity-down package substrates warp in a concave configuration. Die-up package substrates warp in a convex configuration. Increase in temperatures up to 240/spl deg/C had an insignificant effect on the warpage of cavity-down substrates, whereas the die-up package substrate warpage improved with increasing temperature. However, the die-up substrates reverted to their original warpage upon cooling. The sum of the warpage and the ball diameter variation account for almost all the non-planarity. The packages with worse coplanarities showed invariably worse warpages. Substrate warpage of 4 mils or less is required for the successful assembly of PBGA packages. Since cavity-down packages do not show any improvement with increasing temperature, package non-planarity should be less than 7 mils by the seating plane method to ensure less than 4 mils of warpage. The assembly processes can tolerate higher levels of coplanarity for die-up packages as warpage improves at reflow temperatures. It is recommended that the coplanarity be measured by the seating plane method.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114641364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626895
D. Michelson
Known Good Die (KGD) methodology is a process used in the manufacture of semiconductor chips which determines reject limits for parameters measured at sample probe. The philosophy of KGD is to set reject limits on all sample probe parameters at x~/spl plusmn/4 s, where x~ is the sample average and s is the sample standard deviation, assuming a normal distribution on the parameter. When the distribution of measurements is normal, limits set at /spl plusmn/4 s correspond to a C/sub pk/ of 1.33. If the distribution of measurements is not normal, we examine using a generalized C/sub pk/ formula to find the KGD limits. KGD methods are also used to set limits at circuit probe and final test, after the chip has been packaged.
{"title":"Statistically calculating reject limits at parametric test","authors":"D. Michelson","doi":"10.1109/IEMT.1997.626895","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626895","url":null,"abstract":"Known Good Die (KGD) methodology is a process used in the manufacture of semiconductor chips which determines reject limits for parameters measured at sample probe. The philosophy of KGD is to set reject limits on all sample probe parameters at x~/spl plusmn/4 s, where x~ is the sample average and s is the sample standard deviation, assuming a normal distribution on the parameter. When the distribution of measurements is normal, limits set at /spl plusmn/4 s correspond to a C/sub pk/ of 1.33. If the distribution of measurements is not normal, we examine using a generalized C/sub pk/ formula to find the KGD limits. KGD methods are also used to set limits at circuit probe and final test, after the chip has been packaged.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117297733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626876
Yuan Li
Organic solderability preservatives (OSP) are regarded as an excellent pad finish for fine pitch SMT because they can produce a very thin and even coating. However, OSP coatings are more vulnerable to the thermal, humidity and physical effects compared to the HASL coating. In this study, a designed experiment was carried out to systematically study the effects of seven factors on solderability of OSP coated PCBs. These factors included PCB handling, shelf life, prebake atmosphere, dry temperature during cleaning, time delay between cleaning of the first-side misprint and re-print, and hold time between soldering operations. The results of analyzing the experiment data have shown that hold time between soldering operations is the most significant factor; prebake atmosphere when prebake is necessary, bare PCB handling, and dry temperature during cleaning of the first-side misprint are also significant; and within their selected ranges used in the experiment, shelf life, time delay between cleaning of the first-side misprint and re-print, and dry temperature during cleaning after one reflow are not significant. The effect of the water solvent used in the aqueous cleaner on the removal of the OSP coating was also quantified by an additional experiment.
{"title":"An experimental study on organic solderability preservative","authors":"Yuan Li","doi":"10.1109/IEMT.1997.626876","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626876","url":null,"abstract":"Organic solderability preservatives (OSP) are regarded as an excellent pad finish for fine pitch SMT because they can produce a very thin and even coating. However, OSP coatings are more vulnerable to the thermal, humidity and physical effects compared to the HASL coating. In this study, a designed experiment was carried out to systematically study the effects of seven factors on solderability of OSP coated PCBs. These factors included PCB handling, shelf life, prebake atmosphere, dry temperature during cleaning, time delay between cleaning of the first-side misprint and re-print, and hold time between soldering operations. The results of analyzing the experiment data have shown that hold time between soldering operations is the most significant factor; prebake atmosphere when prebake is necessary, bare PCB handling, and dry temperature during cleaning of the first-side misprint are also significant; and within their selected ranges used in the experiment, shelf life, time delay between cleaning of the first-side misprint and re-print, and dry temperature during cleaning after one reflow are not significant. The effect of the water solvent used in the aqueous cleaner on the removal of the OSP coating was also quantified by an additional experiment.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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