Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626884
R. Danzl, A. McLaurin
The use of concentrated hydrogen peroxide as an agent which etches TiW is well known in the metals industry. Although hydrogen peroxide is used in most semiconductor manufacturing processes, its' application as an etchant for TiW has been limited. Since some Micro-Rel product uses a composite metallization scheme containing a TiW/AlSiCu/TiW sandwich, the bonding pad etch process must include a TiW removal step. Without this step, a residual TiW layer is left on the metal pads causing wire adhesion problems (non-sticks) during the wire bonding processes. Current plasma etch techniques still leave a TiW residue on the aluminum surface. The hydrogen peroxide clean was instituted to minimize the presence of the TiW residue. By inserting this clean as the last step of the pad masking module, a cleaner metal surface was developed. To test the new process, wire pulls were done on product by two separate business units within Medtronic. Results from both areas showed no lifts. Surface analyses of metal bond pads treated with hydrogen peroxide shows a significant decrease in the concentrations of metallic oxides and tungsten. The SEM images of bonding pads show no loss in metal thickness and the metal surface is relative smooth with no trace of TiW visually evident.
{"title":"The use of concentrated hydrogen peroxide for the removal of a TiW ARC from aluminum bond pads","authors":"R. Danzl, A. McLaurin","doi":"10.1109/IEMT.1997.626884","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626884","url":null,"abstract":"The use of concentrated hydrogen peroxide as an agent which etches TiW is well known in the metals industry. Although hydrogen peroxide is used in most semiconductor manufacturing processes, its' application as an etchant for TiW has been limited. Since some Micro-Rel product uses a composite metallization scheme containing a TiW/AlSiCu/TiW sandwich, the bonding pad etch process must include a TiW removal step. Without this step, a residual TiW layer is left on the metal pads causing wire adhesion problems (non-sticks) during the wire bonding processes. Current plasma etch techniques still leave a TiW residue on the aluminum surface. The hydrogen peroxide clean was instituted to minimize the presence of the TiW residue. By inserting this clean as the last step of the pad masking module, a cleaner metal surface was developed. To test the new process, wire pulls were done on product by two separate business units within Medtronic. Results from both areas showed no lifts. Surface analyses of metal bond pads treated with hydrogen peroxide shows a significant decrease in the concentrations of metallic oxides and tungsten. The SEM images of bonding pads show no loss in metal thickness and the metal surface is relative smooth with no trace of TiW visually evident.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124046097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626940
P. Seidel, J. Canning, S. Mackay
The integrated circuit industry growth will continue to rely on microlithography as a key enabler to drive chip productivity. Current optical lithography methods (i.e. 193 nm) have been projected to have resolving power down to 130 nm CD generation nodes. Beyond this capability there is a strong consensus that a "Next Generation Lithography" (NGL) technology will be needed to continue along SIA Roadmap timelines. Many NGL technologies are candidates for sub-130 nm CD manufacturing. Choosing the technology path with partial data and limited resources by YE 1997 to meet 130 nm/2003 and 100 nm/2007 generation nodes will require a consensus (international) decision process methodology.
{"title":"Beyond refractive optical lithography next generation lithography \"What's after 193 nm?\"","authors":"P. Seidel, J. Canning, S. Mackay","doi":"10.1109/IEMT.1997.626940","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626940","url":null,"abstract":"The integrated circuit industry growth will continue to rely on microlithography as a key enabler to drive chip productivity. Current optical lithography methods (i.e. 193 nm) have been projected to have resolving power down to 130 nm CD generation nodes. Beyond this capability there is a strong consensus that a \"Next Generation Lithography\" (NGL) technology will be needed to continue along SIA Roadmap timelines. Many NGL technologies are candidates for sub-130 nm CD manufacturing. Choosing the technology path with partial data and limited resources by YE 1997 to meet 130 nm/2003 and 100 nm/2007 generation nodes will require a consensus (international) decision process methodology.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"67 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114107582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626941
W. Smith, W. Tybula
The mask in lithography is the heart of the resulting image on the semiconductor wafer. The mask defines the image to be transferred to the wafer. The evolution of semiconductor manufacturing has seen masks improve from contact devices, that were good for a few pattern transfers, to projection/reduction masks that can be employed for tens of thousands of transfers. As the shrinking of the device dimensions continues, the challenges of obtaining the required quality mask images increases. Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) are increasing the complexity of the masks and producing finer images. As the Next Generation lithography evolves, additional challenges will face the mask manufacturing professional. This paper is an overview of the requirements for the various types of masks.
{"title":"Photomasks for advanced lithography","authors":"W. Smith, W. Tybula","doi":"10.1109/IEMT.1997.626941","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626941","url":null,"abstract":"The mask in lithography is the heart of the resulting image on the semiconductor wafer. The mask defines the image to be transferred to the wafer. The evolution of semiconductor manufacturing has seen masks improve from contact devices, that were good for a few pattern transfers, to projection/reduction masks that can be employed for tens of thousands of transfers. As the shrinking of the device dimensions continues, the challenges of obtaining the required quality mask images increases. Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) are increasing the complexity of the masks and producing finer images. As the Next Generation lithography evolves, additional challenges will face the mask manufacturing professional. This paper is an overview of the requirements for the various types of masks.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127544664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626882
J. Hughes, G. Neudeck
The traditional local oxidation of silicon (LOCOS) device isolation process is widely used in the semiconductor industry. Yet, as the need for below 0.18 microns and smaller devices increases, the stress induced leakage currents and device spacing of LOCOS becomes a severe limitation. The use of Shallow Trench Isolation (STI) has also been developed. However, recent improvements in the selective epitaxial growth dielectric isolation (SEG-DI) process have provided an alternative device isolation technique. The simpler SEG-DI process allows for higher packing density and reduced leakage current by eliminating stress. The DI-SEG process has been shown to be approximately the same cost as the LOCOS process.
{"title":"The total process cost of selective epitaxial growth (SEG) dielectric isolation process as compared to LOCOS","authors":"J. Hughes, G. Neudeck","doi":"10.1109/IEMT.1997.626882","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626882","url":null,"abstract":"The traditional local oxidation of silicon (LOCOS) device isolation process is widely used in the semiconductor industry. Yet, as the need for below 0.18 microns and smaller devices increases, the stress induced leakage currents and device spacing of LOCOS becomes a severe limitation. The use of Shallow Trench Isolation (STI) has also been developed. However, recent improvements in the selective epitaxial growth dielectric isolation (SEG-DI) process have provided an alternative device isolation technique. The simpler SEG-DI process allows for higher packing density and reduced leakage current by eliminating stress. The DI-SEG process has been shown to be approximately the same cost as the LOCOS process.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125334305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626879
S. K. Ladd
The MCM industry is lacking many of the standards and defined processes necessary for creating effective design systems. Improving these design systems is critical to the industry's ability to rapidly launch manufacturable products into the market. Significant efforts must be made to overcome major shortcomings in industry infrastructure, concurrent engineering, expertise, and design tools. MCM design requires many elements of both integrated circuit (IC) and printed circuit board (PCB) design. The combination of industry standards and well developed processes has resulted in excellent design systems for developing highly manufacturable products in a timely manner. The current state of MCM design is assessed using the IC design process as a model. Significant industry investment has yielded enormous gains in IC design productivity, time-to-market, and functional costs. The multichip module industry can benefit from similar approaches. The paper gives detailed examples of specific issues concerning modeling components, substrates, and assemblies. Examples of systems for obtaining die data, substrate design rules, and assembly design rules are shown. These examples are from work performed by numerous organizations and are summarized with a snapshot of work on a portable Pentium(R)-based MCM. The results of developing improved MCM design systems will be significant: better products built at lower cost and brought to market quickly.
{"title":"MCM design for manufacturability","authors":"S. K. Ladd","doi":"10.1109/IEMT.1997.626879","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626879","url":null,"abstract":"The MCM industry is lacking many of the standards and defined processes necessary for creating effective design systems. Improving these design systems is critical to the industry's ability to rapidly launch manufacturable products into the market. Significant efforts must be made to overcome major shortcomings in industry infrastructure, concurrent engineering, expertise, and design tools. MCM design requires many elements of both integrated circuit (IC) and printed circuit board (PCB) design. The combination of industry standards and well developed processes has resulted in excellent design systems for developing highly manufacturable products in a timely manner. The current state of MCM design is assessed using the IC design process as a model. Significant industry investment has yielded enormous gains in IC design productivity, time-to-market, and functional costs. The multichip module industry can benefit from similar approaches. The paper gives detailed examples of specific issues concerning modeling components, substrates, and assemblies. Examples of systems for obtaining die data, substrate design rules, and assembly design rules are shown. These examples are from work performed by numerous organizations and are summarized with a snapshot of work on a portable Pentium(R)-based MCM. The results of developing improved MCM design systems will be significant: better products built at lower cost and brought to market quickly.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125589522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626937
G. A. Riley
While research on adhesive flip chip interconnection is growing rapidly, there has been little information available about how to apply this research to making practical adhesive flip chip assemblies. This paper describes two techniques- stenciled adhesive assembly, and dipped adhesive assembly- of the several available for flip chip interconnections between chip and substrate. Key features and differences of the two methods are discussed and illustrated with examples. The relative advantages, disadvantages, and limitations of the two methods are compared.
{"title":"Adhesive flip chip assembly using plated bump chips","authors":"G. A. Riley","doi":"10.1109/IEMT.1997.626937","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626937","url":null,"abstract":"While research on adhesive flip chip interconnection is growing rapidly, there has been little information available about how to apply this research to making practical adhesive flip chip assemblies. This paper describes two techniques- stenciled adhesive assembly, and dipped adhesive assembly- of the several available for flip chip interconnections between chip and substrate. Key features and differences of the two methods are discussed and illustrated with examples. The relative advantages, disadvantages, and limitations of the two methods are compared.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116539249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626865
C. Beddingfield, L. Higgins
This paper will discuss the non-proprietary aspects of the work-in-progress regarding developments in flux materials to improve the moisture-induced stress sensitivity of Flip Chip Plastic Ball Grid Array devices. Studies addressing the moisture characterization and pre-conditioning, using JEDEC Level 3, of assemblies built with four proprietary fluxes and two alternative underfill materials will be presented, This report includes the evaluation of the weight loss during a simulated die attach reflow profile for each flux type using thermogravimetric analysis. Also, the underfill adhesion strength to the die surface after assembly, after moisture preconditioning and after 48 hours of autoclave stressing will be discussed. The integrity of the solder joint corresponding to each flux type and measured using die pull techniques will also be presented. The effects of the experimental variables on underfill to die/substrate adhesion will also be reveiwed using C-SAM imaging methods.
{"title":"The effects of flux materials on the moisture sensitivity and reliability of flip chip on board assemblies","authors":"C. Beddingfield, L. Higgins","doi":"10.1109/IEMT.1997.626865","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626865","url":null,"abstract":"This paper will discuss the non-proprietary aspects of the work-in-progress regarding developments in flux materials to improve the moisture-induced stress sensitivity of Flip Chip Plastic Ball Grid Array devices. Studies addressing the moisture characterization and pre-conditioning, using JEDEC Level 3, of assemblies built with four proprietary fluxes and two alternative underfill materials will be presented, This report includes the evaluation of the weight loss during a simulated die attach reflow profile for each flux type using thermogravimetric analysis. Also, the underfill adhesion strength to the die surface after assembly, after moisture preconditioning and after 48 hours of autoclave stressing will be discussed. The integrity of the solder joint corresponding to each flux type and measured using die pull techniques will also be presented. The effects of the experimental variables on underfill to die/substrate adhesion will also be reveiwed using C-SAM imaging methods.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131658803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626927
G. Grossmann, L. Weber
The introduction of new packages as well as the ongoing miniaturisation in SMT make the evaluation of the reliability of solder joints a permanent task. Passive thermal cycling is an important test to evaluate the lifetime of solder joints. However, tin-lead solder behaves viscoplastically. Therefore it is mandatory to take the metallurgical behaviour of the solder into account when accelerated tests are designed. Two different deformation mechanisms occur, depending on the temperatures of the test as well as the temperature gradient: grain boundary sliding (GBS) and dislocation climb (DC). Therefore, one is not free in choosing the parameters of a test cycle because test parameters (temperature ramp, dwell time) have a major influence on the growth of cracks. Furthermore the stress under service conditions must be taken into account.
{"title":"Lifetime assessment of soft solder joints on the base of the metallurgical behaviour of Sn/sub 62/Pb/sub 36/Ag/sub 2/","authors":"G. Grossmann, L. Weber","doi":"10.1109/IEMT.1997.626927","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626927","url":null,"abstract":"The introduction of new packages as well as the ongoing miniaturisation in SMT make the evaluation of the reliability of solder joints a permanent task. Passive thermal cycling is an important test to evaluate the lifetime of solder joints. However, tin-lead solder behaves viscoplastically. Therefore it is mandatory to take the metallurgical behaviour of the solder into account when accelerated tests are designed. Two different deformation mechanisms occur, depending on the temperatures of the test as well as the temperature gradient: grain boundary sliding (GBS) and dislocation climb (DC). Therefore, one is not free in choosing the parameters of a test cycle because test parameters (temperature ramp, dwell time) have a major influence on the growth of cracks. Furthermore the stress under service conditions must be taken into account.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134082706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626881
F. Lavallart, N. Cooper
Statistical Machine Control (SMC) encompasses the total maintenance effect on equipment. This approach steps far beyond the "fix it" attitude that has often been the understood job of a maintenance technician. SMC incorporates Total Quality Management (TQM) practices, the predictive and preventive maintenance programs. The goal of the program is to maximize uptime while continuing: to reduce variation. Variation has an effect on product yields, and equipment can be a major cause of the total variation in a factory. SMC addresses these concerns, and it requires a change in mind set that takes time, training and a lot of energy to bring to fruition. SMC works if the organization is committed to overcome the stumbling blocks along the way. This paper is illustrated with four practical examples.
{"title":"Statistical machine control: a practical approach to total productive maintenance of semiconductor equipment","authors":"F. Lavallart, N. Cooper","doi":"10.1109/IEMT.1997.626881","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626881","url":null,"abstract":"Statistical Machine Control (SMC) encompasses the total maintenance effect on equipment. This approach steps far beyond the \"fix it\" attitude that has often been the understood job of a maintenance technician. SMC incorporates Total Quality Management (TQM) practices, the predictive and preventive maintenance programs. The goal of the program is to maximize uptime while continuing: to reduce variation. Variation has an effect on product yields, and equipment can be a major cause of the total variation in a factory. SMC addresses these concerns, and it requires a change in mind set that takes time, training and a lot of energy to bring to fruition. SMC works if the organization is committed to overcome the stumbling blocks along the way. This paper is illustrated with four practical examples.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132120893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626947
K. Yamanaka, H. Mori, Y. Tsukada
A flip chip bonding on a buildup Printed Circuit Board (PCB) has been emerging in a chip carrier area. As chip performance has been improving rapidly, it is now required to have a high performance chip carrier. This paper demonstrates a Ball Grid Array (BGA) application where a flip chip bonding on a multiple buildup layer PCB has an essential electrical performance for a high performance chip which has more than 1000 I/Os and more than 128 bit bus operating at 100 MHz. The effect of a ground plane and a power/ground pick up path design on crosstalk and ground bounce is discussed using SLC-BGA. Also discussed is a package electrical performance comparing various package types. We conclude that flip chip bonding on multiple buildup layer PCB technology is essential for a high performance chip carrier.
{"title":"High performance ball grid array utilizing flip chip bonding on buildup printed circuit board","authors":"K. Yamanaka, H. Mori, Y. Tsukada","doi":"10.1109/IEMT.1997.626947","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626947","url":null,"abstract":"A flip chip bonding on a buildup Printed Circuit Board (PCB) has been emerging in a chip carrier area. As chip performance has been improving rapidly, it is now required to have a high performance chip carrier. This paper demonstrates a Ball Grid Array (BGA) application where a flip chip bonding on a multiple buildup layer PCB has an essential electrical performance for a high performance chip which has more than 1000 I/Os and more than 128 bit bus operating at 100 MHz. The effect of a ground plane and a power/ground pick up path design on crosstalk and ground bounce is discussed using SLC-BGA. Also discussed is a package electrical performance comparing various package types. We conclude that flip chip bonding on multiple buildup layer PCB technology is essential for a high performance chip carrier.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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