Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626875
K. Hikasa, H. Irie
Furukawa Electric has developed method of eluding high-purity solder directly onto fine-pitch contacts through lattice substitution, called Super Solder (SS). The technology has already been adopted in precoating for boards mounting Pentium chips. SS supplies solder to fine-pitch electrode pads through a very simple process consisting of paste coat and heating, and is well suited to the needs of bump formation, especially on boards. This paper covers the configuration and characteristics of a production line providing fully-automatic bump formation with high yield, low labor requirements, and at a low capital investment.
{"title":"Advanced solder bumping technology through super solder","authors":"K. Hikasa, H. Irie","doi":"10.1109/IEMT.1997.626875","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626875","url":null,"abstract":"Furukawa Electric has developed method of eluding high-purity solder directly onto fine-pitch contacts through lattice substitution, called Super Solder (SS). The technology has already been adopted in precoating for boards mounting Pentium chips. SS supplies solder to fine-pitch electrode pads through a very simple process consisting of paste coat and heating, and is well suited to the needs of bump formation, especially on boards. This paper covers the configuration and characteristics of a production line providing fully-automatic bump formation with high yield, low labor requirements, and at a low capital investment.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEMT.1997.626892
P.D. Chalmer
The USEPA's Office of Enforcement and Compliance Assurance (OECA) is sponsoring the creation of National Compliance Assistance Centers for several key industry sectors. The mission of these centers is to provide access to all information which may be useful in helping organizations in each sector attain full environmental compliance. Such a Center is now being established for the printed wiring board (PWB) industry. Information will be primarily delivered through a website. This paper presents an overview of the range of content and type of presentation format possible for the website, along with an invitation to all those involved in PWB manufacturing to participate in fashioning a center which will best suit their needs.
{"title":"The National Printed Wiring Board Resource Center","authors":"P.D. Chalmer","doi":"10.1109/IEMT.1997.626892","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626892","url":null,"abstract":"The USEPA's Office of Enforcement and Compliance Assurance (OECA) is sponsoring the creation of National Compliance Assistance Centers for several key industry sectors. The mission of these centers is to provide access to all information which may be useful in helping organizations in each sector attain full environmental compliance. Such a Center is now being established for the printed wiring board (PWB) industry. Information will be primarily delivered through a website. This paper presents an overview of the range of content and type of presentation format possible for the website, along with an invitation to all those involved in PWB manufacturing to participate in fashioning a center which will best suit their needs.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122697097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEMT.1997.626933
G. Tóth, R.W. Hyora
Electronic product companies (OEMs) face difficult problems today when dealing with the many divergent demand of bringing new products to market. These demands include: Higher system performance; greater feature set; reduced costs; reduced size and weight. Responding to these demands, engineers are increasingly turning to advanced packaging technologies for solutions. However, the best results from these technologies are often obtained only when non-traditional design approaches are used. Designers often overlook valuable resources when they are first exploring advanced packaging alternatives-contract manufacturers. Many of them are experienced with a variety of these technologies and offer their customers design services as well as production services.
{"title":"Using contract manufacturing services to assist with design solutions in advanced packaging technologies","authors":"G. Tóth, R.W. Hyora","doi":"10.1109/IEMT.1997.626933","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626933","url":null,"abstract":"Electronic product companies (OEMs) face difficult problems today when dealing with the many divergent demand of bringing new products to market. These demands include: Higher system performance; greater feature set; reduced costs; reduced size and weight. Responding to these demands, engineers are increasingly turning to advanced packaging technologies for solutions. However, the best results from these technologies are often obtained only when non-traditional design approaches are used. Designers often overlook valuable resources when they are first exploring advanced packaging alternatives-contract manufacturers. Many of them are experienced with a variety of these technologies and offer their customers design services as well as production services.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEMT.1997.626909
R. Schueller
This paper outlines a few of the more promising chip scale package configurations and discusses where they stand with respect to some of the ideal requirements for a CSP. These criteria are: low cost, a good fit to the infrastructure, and excellent board level reliability. Measured against these criteria, none of these packages has emerged as a clear winner. This paper will address a new patent pending chip scale package concept which has low cost potential, uses conventional wire bonding and overmolding processes and has been predicted through mechanical modeling to have excellent board level reliability. Instead of using an elastomeric interposer which decouples the stress of the die from the board, the strategy is to minimize the solder joint stress by instead incorporating a copper interposer which has a matching CTE to that of the board. The die is directly attached to the copper interposer using a standard low stress die attach adhesive. The carrier is supplied in a rigid strip format which can be easily handled with the conventional industry infrastructure. This package is currently being assembled for both a cavity up configuration (peripheral wire bonding to the die) and a cavity down variety (central bonding to the die, ex. DRAM).
{"title":"New chip scale package with CTE matching to the board","authors":"R. Schueller","doi":"10.1109/IEMT.1997.626909","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626909","url":null,"abstract":"This paper outlines a few of the more promising chip scale package configurations and discusses where they stand with respect to some of the ideal requirements for a CSP. These criteria are: low cost, a good fit to the infrastructure, and excellent board level reliability. Measured against these criteria, none of these packages has emerged as a clear winner. This paper will address a new patent pending chip scale package concept which has low cost potential, uses conventional wire bonding and overmolding processes and has been predicted through mechanical modeling to have excellent board level reliability. Instead of using an elastomeric interposer which decouples the stress of the die from the board, the strategy is to minimize the solder joint stress by instead incorporating a copper interposer which has a matching CTE to that of the board. The die is directly attached to the copper interposer using a standard low stress die attach adhesive. The carrier is supplied in a rigid strip format which can be easily handled with the conventional industry infrastructure. This package is currently being assembled for both a cavity up configuration (peripheral wire bonding to the die) and a cavity down variety (central bonding to the die, ex. DRAM).","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131118684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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