Techniques are described for simulating lossy (RLC) transmission lines based on the method of characteristics. For uncoupled lossy transmission lines, a method is presented which speeds up the simulation time by a factor of two compared with existing techniques. A method is also presented for the transient analysis of coupled lossy lines in an inhomogeneous medium. Previously, simulation techniques were limited to coupled lossy lines in a homogeneous medium.<>
{"title":"Improved methods of simulating RLC coupled and uncoupled transmission lines based on the method of characteristics","authors":"Carol V. Gura, J. Abraham","doi":"10.1109/DAC.1988.14774","DOIUrl":"https://doi.org/10.1109/DAC.1988.14774","url":null,"abstract":"Techniques are described for simulating lossy (RLC) transmission lines based on the method of characteristics. For uncoupled lossy transmission lines, a method is presented which speeds up the simulation time by a factor of two compared with existing techniques. A method is also presented for the transient analysis of coupled lossy lines in an inhomogeneous medium. Previously, simulation techniques were limited to coupled lossy lines in a homogeneous medium.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133244778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The algorithms and the implementation of a novel macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the area around the individual cells is determined using novel interconnect area estimator. The second stage consists of: (1) a channel definition step, using a novel channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect-length savings of 8 to 49% were achieved in experiments on nine industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56% versus a variety of other placement methods.<>
{"title":"Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing","authors":"C. Sechen","doi":"10.1109/DAC.1988.14737","DOIUrl":"https://doi.org/10.1109/DAC.1988.14737","url":null,"abstract":"The algorithms and the implementation of a novel macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the area around the individual cells is determined using novel interconnect area estimator. The second stage consists of: (1) a channel definition step, using a novel channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect-length savings of 8 to 49% were achieved in experiments on nine industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56% versus a variety of other placement methods.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. A model is presented for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks for the placement of general cells.<>
{"title":"A new area and shape function estimation technique for VLSI layouts","authors":"Gerhard Zimmerman","doi":"10.1109/DAC.1988.14735","DOIUrl":"https://doi.org/10.1109/DAC.1988.14735","url":null,"abstract":"Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. A model is presented for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks for the placement of general cells.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122293115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tool for synthesizing systolic systems is introduced. Given a hierarchical specification of the computations to be performed and hints as to how, this tool generates an analysis of the hardware required to the computations. The computations are specified as directed acyclic graphs, and the hints provide the temporal and topological relationships of each computation. The systolic system is synthesized by traversing the graph and marking each computation with a processor name and a time stamp. Its output can subsequently be fed to the remaining tools in the tool set to generate a VLSI fabrication description of the systolic system.<>
{"title":"DECOMPOSER: a synthesizer for systolic systems","authors":"Pao-Po Hou, R. Owens, M. J. Irwin","doi":"10.1109/DAC.1988.14835","DOIUrl":"https://doi.org/10.1109/DAC.1988.14835","url":null,"abstract":"A tool for synthesizing systolic systems is introduced. Given a hierarchical specification of the computations to be performed and hints as to how, this tool generates an analysis of the hardware required to the computations. The computations are specified as directed acyclic graphs, and the hints provide the temporal and topological relationships of each computation. The systolic system is synthesized by traversing the graph and marking each computation with a processor name and a time stamp. Its output can subsequently be fed to the remaining tools in the tool set to generate a VLSI fabrication description of the systolic system.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125075259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Odawara, M. Tomita, Kazuhiko Hattori, O. Okuzawa, Toshiaki Hirata, M. Ochiai
A description is given of a novel human-machine interface for use as a design environment for silicon compilation. It is important for a human machine interface to support a tool which realizes quick turn around time with little possibility of user errors. Designers should be able to work with little interference with their thinking process. To realize such a design environment, the authors have developed an LCD digitizer, and it has been demonstrated that this device can be a designer-friendly human-machine interface.<>
{"title":"A human machine interface for silicon compilation","authors":"G. Odawara, M. Tomita, Kazuhiko Hattori, O. Okuzawa, Toshiaki Hirata, M. Ochiai","doi":"10.1109/DAC.1988.14745","DOIUrl":"https://doi.org/10.1109/DAC.1988.14745","url":null,"abstract":"A description is given of a novel human-machine interface for use as a design environment for silicon compilation. It is important for a human machine interface to support a tool which realizes quick turn around time with little possibility of user errors. Designers should be able to work with little interference with their thinking process. To realize such a design environment, the authors have developed an LCD digitizer, and it has been demonstrated that this device can be a designer-friendly human-machine interface.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author proposes a semantic network plus model (SN/sup +/M) as a data model for an integrated CAD/CAM (computer-aided-design/computer-aided-manufacturing) database system. SN/sup +/M basically is a model coupling semantic network capability developed in artificial intelligence and relational table capability developed in database management to naturally accommodate the features of a complex data domain. He discusses some of the special features of a CAD/CAM data domain which make it very desirable to have a higher-level data model. The SN/sup +/M data model concept is then briefly discussed. He also discusses how the model can be applied to some of the important and representative data of the CAD/CAM domain. Finally, he summarizes the major advantages of SN/sup +/M as compared with conventional data models.<>
{"title":"An enhanced data model for CAD/CAM database systems","authors":"Ying-Kuei Yang","doi":"10.1109/DAC.1988.14768","DOIUrl":"https://doi.org/10.1109/DAC.1988.14768","url":null,"abstract":"The author proposes a semantic network plus model (SN/sup +/M) as a data model for an integrated CAD/CAM (computer-aided-design/computer-aided-manufacturing) database system. SN/sup +/M basically is a model coupling semantic network capability developed in artificial intelligence and relational table capability developed in database management to naturally accommodate the features of a complex data domain. He discusses some of the special features of a CAD/CAM data domain which make it very desirable to have a higher-level data model. The SN/sup +/M data model concept is then briefly discussed. He also discusses how the model can be applied to some of the important and representative data of the CAD/CAM domain. Finally, he summarizes the major advantages of SN/sup +/M as compared with conventional data models.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129040356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MOZART is a concurrent fault simulator for large circuits described in the RT, functional gate, and switch levels. Performance is gained by means of techniques aimed at the reduction of unnecessary activity. Two such techniques are levelized two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active faulty machines can dramatically improve fault simulator performance. These and related issues are discussed, and analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A novel performance metric is introduced for fault simulation that is based on comparison with the serial algorithm and is more accurate than those currently used.<>
{"title":"The performance of the concurrent fault simulation algorithms in MOZART","authors":"S. Gai, P. Montessoro, F. Somenzi","doi":"10.1109/DAC.1988.14844","DOIUrl":"https://doi.org/10.1109/DAC.1988.14844","url":null,"abstract":"MOZART is a concurrent fault simulator for large circuits described in the RT, functional gate, and switch levels. Performance is gained by means of techniques aimed at the reduction of unnecessary activity. Two such techniques are levelized two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active faulty machines can dramatically improve fault simulator performance. These and related issues are discussed, and analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A novel performance metric is introduced for fault simulation that is based on comparison with the serial algorithm and is more accurate than those currently used.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem of verifying the correctness of a combinatorial design is known to be NP-complete. Nevertheless, most products reaching the consumer are functionally correct. The author attempts to explain this phenomenon by considering the effort of going through a less-than-perfect design-verification process and then explains why many design errors are relatively easily caught.<>
{"title":"Why partial design verification works better than it should","authors":"J. Savir","doi":"10.1109/DAC.1988.14846","DOIUrl":"https://doi.org/10.1109/DAC.1988.14846","url":null,"abstract":"The problem of verifying the correctness of a combinatorial design is known to be NP-complete. Nevertheless, most products reaching the consumer are functionally correct. The author attempts to explain this phenomenon by considering the effort of going through a less-than-perfect design-verification process and then explains why many design errors are relatively easily caught.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115824436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A mechanism for integrated simulators into CAD (computer-aided design) systems have been implemented to provide high-performance interaction during the course of the design. This mechanism replaces slow text-based interfaces by a persistent programming technique where the database is viewed as an extension of dynamically allocated memory. Organization of simulation data and implementation of the interface mechanism are described.<>
{"title":"The architecture of a highly integrated simulation system","authors":"M. Heydemann, Alain Plaignaud, D. Dure","doi":"10.1109/DAC.1988.14828","DOIUrl":"https://doi.org/10.1109/DAC.1988.14828","url":null,"abstract":"A mechanism for integrated simulators into CAD (computer-aided design) systems have been implemented to provide high-performance interaction during the course of the design. This mechanism replaces slow text-based interfaces by a persistent programming technique where the database is viewed as an extension of dynamically allocated memory. Organization of simulation data and implementation of the interface mechanism are described.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123474514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simulated annealing schedule is derived. Its application to the standard cell placement and the traveling salesman problems results in a two to twenty-four times speedup over annealing schedules currently available in the literature. Since it uses only statistical quantities, the annealing schedule is applicable to general combinatorial optimization problems.<>
{"title":"Performance of a new annealing schedule","authors":"Jimmy Lam, J. Delosme","doi":"10.1109/DAC.1988.14775","DOIUrl":"https://doi.org/10.1109/DAC.1988.14775","url":null,"abstract":"A simulated annealing schedule is derived. Its application to the standard cell placement and the traveling salesman problems results in a two to twenty-four times speedup over annealing schedules currently available in the literature. Since it uses only statistical quantities, the annealing schedule is applicable to general combinatorial optimization problems.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：