Channel routing area improvement by means of via minimization and via shifting in two dimensions (compaction) is readily achievable. Routing feature area can be minimized by wire straightening. The implementation of algorithms for each of these procedures has produced a solution for D.N. Deutsch's (1985) Difficult Example, the standard channel routing benchmark, that is more than 5% smaller than the best result published heretofore. Suggestions for possible future work are given.<>
{"title":"Improved channel routing by via minimization and shifting","authors":"Chung-Kuan Cheng, D. Deutsch","doi":"10.1109/DAC.1988.14841","DOIUrl":"https://doi.org/10.1109/DAC.1988.14841","url":null,"abstract":"Channel routing area improvement by means of via minimization and via shifting in two dimensions (compaction) is readily achievable. Routing feature area can be minimized by wire straightening. The implementation of algorithms for each of these procedures has produced a solution for D.N. Deutsch's (1985) Difficult Example, the standard channel routing benchmark, that is more than 5% smaller than the best result published heretofore. Suggestions for possible future work are given.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"62 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128452486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm called the O-algorithm is introduced for automatic test program generation of microprocessors in a user environment. To eliminate redundant tests, a weight-digraph model is used to model the signal flow of the general microprocessors. Improved functional fault models of microprocessors are derived from the Turing machine model. The O-algorithm is then constructed on the basis of the signal flow model and functional fault models. Simulation has shown that the fault coverage is better than 97%.<>
{"title":"Automatic functional test program generation for microprocessors","authors":"Chen-Shang Lin, Hong-Fa Ho","doi":"10.1109/DAC.1988.14825","DOIUrl":"https://doi.org/10.1109/DAC.1988.14825","url":null,"abstract":"An algorithm called the O-algorithm is introduced for automatic test program generation of microprocessors in a user environment. To eliminate redundant tests, a weight-digraph model is used to model the signal flow of the general microprocessors. Improved functional fault models of microprocessors are derived from the Turing machine model. The O-algorithm is then constructed on the basis of the signal flow model and functional fault models. Simulation has shown that the fault coverage is better than 97%.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115778023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Motohara, Motohide Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano
The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed.<>
{"title":"An approach to fast hierarchical fault simulation","authors":"A. Motohara, Motohide Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano","doi":"10.1109/DAC.1988.14845","DOIUrl":"https://doi.org/10.1109/DAC.1988.14845","url":null,"abstract":"The authors present an approach to hierarchical fault simulation which generates several simulation models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes lookup tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective in improving simulation speed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115338941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.<>
{"title":"An automated BIST approach for general sequential logic synthesis","authors":"C. Stroud","doi":"10.1109/DAC.1988.14726","DOIUrl":"https://doi.org/10.1109/DAC.1988.14726","url":null,"abstract":"An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.<>
{"title":"For incremental circuit analysis using extracted hierarchy","authors":"D. Beatty, R. Bryant","doi":"10.1109/DAC.1988.14805","DOIUrl":"https://doi.org/10.1109/DAC.1988.14805","url":null,"abstract":"The authors present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126009774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input. The authors extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at-tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.<>
{"title":"A method of delay fault test generation","authors":"C. Glover, M. R. Mercer","doi":"10.1109/DAC.1988.14740","DOIUrl":"https://doi.org/10.1109/DAC.1988.14740","url":null,"abstract":"The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input. The authors extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at-tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123498684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional automatic layout systems for MOS or bipolar devices systems cannot deal with certain features, e.g. signal serialization, in serial routing devices such as Josephson devices. The authors define layout requirements and present new automatic layout procedures for such devices. These procedures are based on it subnet partitioning. They can be applied to the hierarchical design of both masterslice and custom logic LSIs. Experiments using four-bit-full-adder circuits confirm their feasibility.<>
{"title":"Automatic layout procedures for serial routing devices","authors":"Y. Ogawa, H. Terai, T. Kozawa","doi":"10.1109/DAC.1988.14833","DOIUrl":"https://doi.org/10.1109/DAC.1988.14833","url":null,"abstract":"Conventional automatic layout systems for MOS or bipolar devices systems cannot deal with certain features, e.g. signal serialization, in serial routing devices such as Josephson devices. The authors define layout requirements and present new automatic layout procedures for such devices. These procedures are based on it subnet partitioning. They can be applied to the hierarchical design of both masterslice and custom logic LSIs. Experiments using four-bit-full-adder circuits confirm their feasibility.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal solutions for the smaller problems into a near-optimal solution for the original placement problem. The algorithm lends itself very naturally to a parallel realization, and maps nicely onto an SIMD (single-instruction, multiple data-stream) organization. Considerations such as cost-effectiveness and suitability to VLSI implementation led to the selection of the reduced array architecture as the target architecture for the placement accelerator.<>
{"title":"Parallel placement on reduced array architecture","authors":"C. Ravikumar, S. Sastry","doi":"10.1109/DAC.1988.14746","DOIUrl":"https://doi.org/10.1109/DAC.1988.14746","url":null,"abstract":"The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal solutions for the smaller problems into a near-optimal solution for the original placement problem. The algorithm lends itself very naturally to a parallel realization, and maps nicely onto an SIMD (single-instruction, multiple data-stream) organization. Considerations such as cost-effectiveness and suitability to VLSI implementation led to the selection of the reduced array architecture as the target architecture for the placement accelerator.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). The authors give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs for pipelined designs is used to formulate the problem, and an overview of the solution technique is given. Complexities introduced by nonoptimal designs and user constraints are addressed. The results have been validated using designs generated by an automated pipeline synthesis program.<>
{"title":"Module selection for pipelined synthesis","authors":"R. Jain, A. C. Parker, N. Park","doi":"10.1109/DAC.1988.14813","DOIUrl":"https://doi.org/10.1109/DAC.1988.14813","url":null,"abstract":"module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). The authors give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs for pipelined designs is used to formulate the problem, and an overview of the solution technique is given. Complexities introduced by nonoptimal designs and user constraints are addressed. The results have been validated using designs generated by an automated pipeline synthesis program.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132782338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A data structure for storing and processing electrical circuit net lists is described. The basic data structure is not new, but the version described here is novel in three specific ways. It adds separate structure (arrays) for cell type and I/O-pad-specific information, stores net lists defined in terms of primitive elements or cells as two superimposed symmetric incidence list form directed graphs, and separates primitive element input and output lists to follow signal flow traversal. The focus is on computer-program-level implementation details and on various practical problems arising in circuit net-list processing. The structure's construction cost and algorithmic efficiency are discussed.<>
描述了一种用于存储和处理电路网表的数据结构。基本的数据结构不是新的，但是这里描述的版本在三个特定的方面是新颖的。它为单元类型和I/ o -pad特定信息添加了单独的结构(数组)，将根据基本元素或单元定义的净列表存储为两个重叠的对称关联列表，形成有向图，并将基本元素输入和输出列表分开，以遵循信号流遍历。重点是计算机程序级的实现细节和电路网表处理中出现的各种实际问题。讨论了该结构的造价和算法效率
{"title":"A data structure for circuit net lists","authors":"Steve Meyer","doi":"10.1109/DAC.1988.14827","DOIUrl":"https://doi.org/10.1109/DAC.1988.14827","url":null,"abstract":"A data structure for storing and processing electrical circuit net lists is described. The basic data structure is not new, but the version described here is novel in three specific ways. It adds separate structure (arrays) for cell type and I/O-pad-specific information, stores net lists defined in terms of primitive elements or cells as two superimposed symmetric incidence list form directed graphs, and separates primitive element input and output lists to follow signal flow traversal. The focus is on computer-program-level implementation details and on various practical problems arising in circuit net-list processing. The structure's construction cost and algorithmic efficiency are discussed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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